Power shifting in Thrifty Interconnection Network

This paper presents two complementary techniques to manage the power consumption of large-scale systems with a packet-switched interconnection network. First, we propose Thrifty Interconnection Network (TIN), where the network links are activated and de-activated dynamically with little or no overhead by using inherent system events to timely trigger link activation or de-activation. Second, we propose Network Power Shifting (NPS) that dynamically shifts the power budget between the compute nodes and their corresponding network components. TIN activates and trains the links in the interconnection network, just-in-time before the network communication is about to happen, and thriftily puts them into a low-power mode when communication is finished, hence reducing unnecessary network power consumption. Furthermore, the compute nodes can absorb the extra power budget shifted from its attached network components and increase their processor frequency for higher performance with NPS. Our simulation results on a set of real-world workload traces show that TIN can achieve on average 60% network power reduction, with the support of only one low-power mode. When NPS is enabled, the two together can achieve 12% application performance improvement and 13% overall system energy reduction. Further performance improvement is possible if the compute nodes can speed up more and fully utilize the extra power budget reinvested from the thrifty network with more aggressive cooling support.

[1]  Jian Li,et al.  A framework for end-to-end simulation of high-performance computing systems , 2008, Simutools 2008.

[2]  Benton H. Calhoun,et al.  Power switch characterization for fine-grained dynamic voltage scaling , 2008, 2008 IEEE International Conference on Computer Design.

[3]  Darren J. Kerbyson,et al.  A General Performance Model of Structured and Unstructured Mesh Particle Transport Computations , 2005, The Journal of Supercomputing.

[4]  R. C. Malone,et al.  Parallel ocean general circulation modeling , 1992 .

[5]  Pedro López,et al.  A high performance router architecture for interconnection networks , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.

[6]  J. Michalakes,et al.  Design of a next-generation regional weather research and forecast model. , 1999 .

[7]  Li-Shiuan Peh,et al.  Design-space exploration of power-aware on/off interconnection networks , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[8]  Mahmut T. Kandemir,et al.  Energy optimization techniques in cluster interconnects , 2003, ISLPED '03.

[9]  Mike Ignatowski,et al.  Exploitation of optical interconnects in future server architectures , 2005, IBM J. Res. Dev..

[10]  Thomas F. Wenisch,et al.  Power routing: dynamic power provisioning in the data center , 2010, ASPLOS XV.

[11]  B. C. Curtis,et al.  Very High Resolution Simulation of Compressible Turbulence on the IBM-SP System , 1999, ACM/IEEE SC 1999 Conference (SC'99).

[12]  D.K. Lowenthal,et al.  Adaptive, Transparent Frequency and Voltage Scaling of Communication Phases in MPI Programs , 2006, ACM/IEEE SC 2006 Conference (SC'06).

[13]  William J. Dally,et al.  Technology-Driven, Highly-Scalable Dragonfly Topology , 2008, 2008 International Symposium on Computer Architecture.

[14]  Li Shang,et al.  Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[15]  Pedro López,et al.  Power saving in regular interconnection networks built with high-degree switches , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[16]  Chita R. Das,et al.  ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[17]  Ahmed Louri,et al.  iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures , 2008, 2008 International Symposium on Computer Architecture.

[18]  J. Koomey,et al.  Report to Congress on Server and Data Center Energy Efficiency: Public Law 109-431: Appendices , 2008 .

[19]  Mark R. Fahey,et al.  GYRO: A 5-D Gyrokinetic-Maxwell Solver , 2004, Proceedings of the ACM/IEEE SC2004 Conference.

[20]  Kevin J. Nowka,et al.  Dynamic Power Management by Combination of Dual Static Supply Voltages , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[21]  Karthick Rajamani,et al.  A performance-conserving approach for reducing peak power consumption in server systems , 2005, ICS '05.

[22]  Torsten Hoefler,et al.  The PERCS High-Performance Interconnect , 2010, 2010 18th IEEE Symposium on High Performance Interconnects.

[23]  Steve Plimpton,et al.  Fast parallel algorithms for short-range molecular dynamics , 1993 .

[24]  Holger Gohlke,et al.  The Amber biomolecular simulation programs , 2005, J. Comput. Chem..

[25]  William J. Dally,et al.  Flit-reservation flow control , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[26]  Meeta Sharma Gupta,et al.  System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[27]  Min Yeol Lim,et al.  MPI and communication - Adaptive, transparent frequency and voltage scaling of communication phases in MPI programs , 2006, SC.

[28]  Pedro López,et al.  Dynamic power saving in fat-tree interconnection networks using on/off links , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[29]  Jian Li,et al.  A Framework for End-to-End Simulation of High-performance Computing Systems , 2008, Simul..

[30]  Hong Liu,et al.  Energy proportional datacenter networks , 2010, ISCA.