Low power latch based design with smart retiming

Flip-flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology.

[1]  Sandeep K. Gupta,et al.  Structural delay testing of latch-based high-speed pipelines with time borrowing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Takeshi Yoshimura,et al.  Timing optimization by replacing flip-flops to latches , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[3]  Benton H. Calhoun,et al.  Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  David G. Chinnery,et al.  Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design , 2002 .

[5]  David Blaauw,et al.  Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction , 2013, IEEE Journal of Solid-State Circuits.

[6]  Anantha Chandrakasan,et al.  Circuit Styles for Logics , 2001 .

[7]  Benton H. Calhoun,et al.  Hold time closure for subthreshold circuits using a two-phase, latch based timing method , 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[8]  Youngsoo Shin,et al.  Pulser gating: A clock gating of pulsed-latch circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[9]  Youn-Long Lin,et al.  Storage optimization by replacing some flip-flops with latches , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[10]  Doris Schmitt-Landsiedel,et al.  Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[11]  Jochen A. G. Jess,et al.  Analysis and reduction of glitches in synchronous networks , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[12]  Jean-Luc Nagel,et al.  Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation , 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

[13]  Gi-Joon Nam,et al.  Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[14]  M. Okada,et al.  A skew-tolerant design scheme for over 1-GHz LSIs , 2000, Proceedings of the 26th European Solid-State Circuits Conference.