Ultra‐large‐scale integration device scaling and reliability

Assuming that the requisite lithography and planarization techniques will be available, this article reviews the goals of metal–oxide semiconductor field effect transistor (MOSFET) scaling and the constraints of low leakage and adequate reliability, highlighting the impact of power‐supply voltage and oxide thickness reductions. Plasma charging damage is discussed. The first identifiable scaling limit is the direct tunneling of gate oxide at 3.5 nm, which may hinder scaling beyond 0.09 μm. From the 0.5‐μm generation onward, MOSFET current will basically cease to increase with scaling. Gate speed will double every four generations rather than two generations of technology as in the past unless technology innovations can pick up the slack.