A capacitorless twin-transistor random access memory (TTRAM) on SOI

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode.

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