Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation

Miniaturisation in modern microprocessors increases susceptibility to soft errors leading to reliability degradation. Recently simultaneous multithreaded (SMT) architecture is utilised to improve fault tolerance. Despite full coverage, redundant checking in such schemes causes significant performance and energy overheads. Fortunately, some of the soft errors can be masked at the architectural level and architectural vulnerability factor (AVF) of a structure represents the portion of soft errors which lead to a failure in the output of a program. In this study, the authors present an infrastructure for online monitoring of AVF of sensitive structures of an SMT processor. Based on estimated AVF, we have introduced partial thread redundancy (PTR) protection scheme for intervals whose AVF is greater than a predefined threshold and the estimated AVF is used for adaptation between reliability improvement or performance enhancement, especially when the processor executes more than one workload. We have utilised SPEC CPU2006 benchmarks for AVF estimation of some important hardware resources such as issue queue, reorder buffer, load/store queue and register file. Experimental results show that the mean absolute error of our AVF estimation method varies from 0.04 to 0.07 and combined online AVF estimation and PTR protection, leads to a reliability aware execution and lower performance overhead.