A novel N-th order IIR switched-capacitor decimator building block with optimum implementation

A novel N-th order infinite-impulse response (IIR) switched-capacitor (SC) decimator building block with optimum implementation has been developed for realizing arbitrary baseband and antialiasing amplitude responses using a minimum number of switching waveforms and operational amplifiers with relaxed speed requirements. Alternative topologies can be adopted, depending on the acceptable capacitance spread and total capacitor area in the circuit as well as the performance under nonideal characteristics of the amplifiers. Practical designs of third-order and fourth-order IIR SC decimator building blocks with different factors of sampling rate reduction are presented for illustration purposes.<<ETX>>