Intra- and inter-circuit network for Petri nets based components

This paper aims to present a development environment that enables the automatic code generation amenable for the interconnection of components obtained as a result of the partition of a Petri net model addressing its distributed execution using networked controllers (including microcontrollers and FPGAs devices, as well as specific controllers based on PLCs and general purpose PCs). The proposed interconnection solution is based on a Network-on-Chip solution supporting communications based on RS-232 serial protocol (although it can operate at higher transmission rates), for intra-circuit as well as inter-circuits interconnectivity. Being a well-accepted protocol in the industry, the proposed solution integrates existing modules that use the RS232 interface without having to redesign the whole communication system. Implementation platforms used for testing solution include Xilinx reconfigurable platforms, namely Spartan3 and Virtex FPGAs, as well as low cost microcontrollers, namely Microchip PIC18F4620, and general purpose PCs; industrial PCs, PLCs or other platforms with an RS-232 serial port can be easily integrated. A ring topology was selected to allow greater flexibility. The proposed architecture and protocol will be described. Finally, an example will be presented where, starting from the Petri nets model, the flow of development will be presented.

[1]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[2]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[3]  Laure Petrucci,et al.  The Petri Net Markup Language: Concepts, Technology, and Tools , 2003, ICATPN.

[4]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[5]  Luis Gomes,et al.  Structuring Mechanisms in Petri Net Models , 2005 .

[6]  L. Gomes,et al.  The Input-Output Place-Transition Petri Net Class and Associated Tools , 2007, 2007 5th IEEE International Conference on Industrial Informatics.

[7]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[8]  Xin Wang,et al.  An On-Chip CDMA Communication Network , 2005, 2005 International Symposium on System-on-Chip.

[9]  Lus Gomes,et al.  Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation , 2009 .

[10]  J. Nurmi,et al.  Reusable XGFT interconnect IP for network-on-chip implementations , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[11]  Jari Nurmi,et al.  Issues in the development of a practical NoC: the Proteo concept , 2004, Integr..

[12]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[13]  Luis Gomes,et al.  Petri net partitioning using net splitting operation , 2009, 2009 7th IEEE International Conference on Industrial Informatics.

[14]  J. Nurmi Network-on-Chip: A New Paradigm for System-on-Chip Design , 2005, 2005 International Symposium on System-on-Chip.