SystemC/TLM flow for SoC design and verification

As systems grow in complexity, their verification becomes a bottleneck on the design flow. In this paper we propose a top-down methodology to perform the complete flow from specifications to Register Transfer Level (RTL). Different abstraction levels such as Transaction Level Modeling (TLM) allows early system verification (with simulation or formal methods), reducing the risk of long redesign cycles. The methodology is validated by showing a case study.

[1]  Frank Ghenassia.  Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .

[2]  Patrick Schaumont,et al.  An object oriented programming approach for hardware design , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[3]  Martin Peschke,et al.  Design and Validation of Computer Protocols , 2003 .

[4]  Rolf Drechsler,et al.  The system verification methodology for advanced TLM verification , 2012, CODES+ISSS '12.

[5]  Florence Maraninchi,et al.  A SystemC/TLM Semantics in Promelaand Its Possible Applications , 2007, SPIN.

[6]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[7]  A. Cortes,et al.  A Transaction Level Assertion Verification Framework in SystemC: An Application Study , 2009, 2009 Second International Conference on Advances in Circuits, Electronics and Micro-electronics.

[8]  Harry Foster.  Why the design productivity gap never happened , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Sofiène Tahar,et al.  Design for verification of SystemC transaction level models , 2005, Design, Automation and Test in Europe.

[10]  Daniel D. Gajski,et al.  SPECC: Specification Language and Methodology , 2000 .

[11]  Edsger W. Dijkstra,et al.  Guarded commands, nondeterminacy and formal derivation of programs , 1975, Commun. ACM.

[12]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[13]  Stan Y. Liao,et al.  YAML: a tool for hardware design visualization and capture , 2000, ISSS '00.

[14]  Robert Wille,et al.  Automated feature localization for dynamically generated SystemC designs , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[15]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[16]  Wolfgang Müller,et al.  Advanced SoC virtual prototyping for system-level power planning and validation , 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[17]  Gerard J. Holzmann,et al.  Coverage Preserving Reduction Strategies for Reachability Analysis , 1992, PSTV.

[18]  William K. Lam.  Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series) , 2005 .

[19]  Wolfgang Müller,et al.  Architectural low-power design using transaction-based system modeling and simulation , 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

[20]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[21]  Ning Wu,et al.  Efficient Synchronization for Distributed Embedded Multiprocessors , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Ralph H. J. M. Otten,et al.  Challenges in physical chip design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).