Wavefront technology mapping

The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly decouples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal delay on directed acyclic graphs (DAGs) when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.

[1]  Kenneth L. Shepard,et al.  Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors , 1997, IBM J. Res. Dev..

[2]  Robert K. Brayton,et al.  Delay-optimal technology mapping by DAG covering , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[3]  Joel Grodstein,et al.  A delay model for logic synthesis of continuously-sized networks , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[4]  P. Kudva,et al.  Gate-size selection for standard cell libraries , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  Ivan E. Sutherland,et al.  Logical effort: designing for speed on the back of an envelope , 1991 .

[6]  K. Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.

[7]  Robert B. Hitchcock,et al.  Timing verification and the timing analysis program , 1988, DAC 1982.

[8]  Yosinori Watanabe,et al.  Logic decomposition during technology mapping , 1995, ICCAD.

[9]  Robert B. Hitchcock,et al.  Timing Verification and the Timing Analysis Program , 1982, 19th Design Automation Conference.

[10]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[11]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[12]  Daniel Brand,et al.  BooleDozer: Logic synthesis for ASICs , 1996, IBM J. Res. Dev..

[13]  Yosinori Watanabe,et al.  A delay model for logic synthesis of continuously-sized networks , 1995, ICCAD.