Experimental evaluation of code properties for WCET analysis

This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units, and out-of-order execution units have on the worst-case execution time (WCET) of programs. These features are present in processors (e.g. PowerPC) that are being widely used in embedded and real-time systems. We present an experimental evaluation of the execution time of a series of synthetic benchmarks and real-life case studies. The execution time is evaluated using extensive testing and a simple WCET technique. We show that the most important factor in reduction of execution time is cache size (both instruction and data cache). Other factors like branch prediction and out-of-order execution have minimal improvements that are cancelled out by the pessimism of the analysis. We also argue that some of the performance gain of advanced processor features also applies to the worst case and although WCET estimates may be more pessimistic the overall impact is that they result in lower WCET estimates.

[1]  Alan Burns,et al.  Pipelined processors and worst case execution times , 1993, Real-Time Systems.

[2]  Jakob Engblom,et al.  Pipeline timing analysis using a trace-driven simulator , 1999, Proceedings Sixth International Conference on Real-Time Computing Systems and Applications. RTCSA'99 (Cat. No.PR00306).

[3]  Tse-Yu Yeh,et al.  Understanding branches and designing branch predictors for high-performance microprocessors , 2001, Proc. IEEE.

[4]  Pascal Sainrat,et al.  Difficulties in Computing the WCET for Processors with Speculative Execution , 2002 .

[5]  Kevin Jeffay,et al.  Predicting Worst Case Execution Times on a Pipelined RISC Processor , 1995 .

[6]  Sharad Malik,et al.  Performance Analysis of Embedded Software Using Implicit Path Enumeration , 1995, 32nd Design Automation Conference.

[7]  Frank Mueller,et al.  Compiler support for software-based cache partitioning , 1995, Workshop on Languages, Compilers, & Tools for Real-Time Systems.

[8]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[9]  Peter P. Puschner,et al.  Calculating the maximum execution time of real-time programs , 1989, Real-Time Systems.

[10]  Friedhelm Stappert,et al.  Complete worst-case execution time analysis of straight-line hard real-time programs , 2000, J. Syst. Archit..

[11]  Isabelle Puaut,et al.  Worst Case Execution Time Analysis for a Processor with Branch Prediction , 2004, Real-Time Systems.

[12]  David B. Whalley,et al.  Timing analysis for data caches and set-associative caches , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[13]  Tulika Mitra,et al.  A Framework to Model Branch Prediction for WCET Analysis , 2002 .

[14]  Jakob Engblom,et al.  Efficient longest executable path search for programs with complex flows and pipeline effects , 2001, CASES '01.

[15]  Guillem Bernat,et al.  pWCET: a Tool for Probabilistic Worst-Case Execution Time Analysis of Real-Time Systems , 2003 .

[16]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[17]  Stefan M. Petters.  Comparison of Trace Generation Methods for Measurement Based WCET Analysis , 2003, WCET.

[18]  Guillem Bernat,et al.  WCET analysis of probabilistic hard real-time systems , 2002, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002..

[19]  Henrik Theiling,et al.  Fast and Precise WCET Prediction by Separated Cache and Path Analyses , 2000, Real-Time Systems.

[20]  David B. Whalley,et al.  Bounding Pipeline and Instruction Cache Performance , 1999, IEEE Trans. Computers.

[21]  Reinhard Wilhelm,et al.  On Predicting Data Cache Behavior for Real-Time Systems , 1998, LCTES.

[22]  Frank Mueller.  Compiler support for software-based cache partitioning , 1995 .

[23]  Frank Müller,et al.  Timing Analysis for Instruction Caches , 2000, Real-Time Systems.

[24]  Isabelle Puaut,et al.  Low-complexity algorithms for static cache locking in multitasking hard real-time systems , 2002, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002..

[25]  Heonshik Shin,et al.  Experimental Assessment of the Period Calibration Method: A Case Study , 1999, Real-Time Systems.

[26]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[27]  Graham R. Nudd,et al.  Analytical Modeling of Set-Associative Cache Behavior , 1999, IEEE Trans. Computers.

[28]  Rolf Ernst,et al.  Data flow based cache prediction using local simulation , 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).

[29]  Jochen Liedtke,et al.  OS-controlled cache predictability for real-time systems , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[30]  Johann Blieberger,et al.  Symbolic Cache Analysis for Real-Time Systems , 2000, Real-Time Systems.

[31]  Sang Lyul Min,et al.  Analysis of the impacts of overestimation sources on the accuracy of worst case timing analysis , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[32]  Sang Lyul Min,et al.  An Accurate Worst Case Timing Analysis for RISC Processors , 1995, IEEE Trans. Software Eng..