Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self-Heating

A physics-based compact model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors including impact ionization, subsequent snapback (SB), and self-heating (SH) is presented. It is observed that the SB effect is caused by the turn-on of the associated parasitic bipolar transistor. The model includes the effect of device SH using resistive thermal networks for each region. Comparisons of modeling results with device simulation data show that, over a wide range of bias voltages, the model exhibits excellent accuracy without any convergence problem.

[1]  S. Takahashi,et al.  An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n/sup +/ diodes , 2004, IEEE Transactions on Electron Devices.

[2]  Gerard Merckel,et al.  Triggering and sustaining of snapback in MOSFETs , 1992 .

[3]  M.S. Adler,et al.  The evolution of power device technology , 1984, IEEE Transactions on Electron Devices.

[4]  Thomas Lackner,et al.  Avalanche multiplication in semiconductors: A modification of Chynoweth's law , 1991 .

[5]  G. Groeseneken,et al.  Analysis of Snapback in Soi nMosfets and its Use for an Soi Esd Protection Circuit , 1992, 1992 IEEE International SOI Conference.

[6]  Roberto Guerrieri,et al.  A new discretization strategy of the semiconductor equations comprising momentum and energy balance , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Adrian M. Ionescu,et al.  Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects , 2006 .

[8]  P.M. Holland,et al.  An Alternative Process Architecture for CMOS Based High Side RESURF LDMOS Transistors , 2006, 2006 25th International Conference on Microelectronics.

[9]  J. Kocsis,et al.  High-voltage integrated circuits , 1969 .

[10]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[11]  Krishna Shenai,et al.  Performance modeling of RF power MOSFETs , 1999 .

[12]  G.J. Coram,et al.  How to (and how not to) write a compact model in Verilog-A , 2004, Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004..

[13]  Florin Udrea,et al.  Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices , 1999 .

[14]  A. O. Adan,et al.  Analytical threshold voltage model for ultrathin SOI MOSFETs including short-channel and floating-body effects , 1999 .

[15]  S. Ramaswamy,et al.  Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations , 1997 .

[16]  M. Darwish,et al.  Study of the quasi-saturation effect in VDMOS transistors , 1986, IEEE Transactions on Electron Devices.

[17]  R. van Langevelde,et al.  A surface-potential-based high-voltage compact LDMOS transistor model , 2005, IEEE Transactions on Electron Devices.

[18]  W. J. Kloosterman,et al.  Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating , 2001 .

[19]  V.A.K. Temple,et al.  Theoretical comparison of DMOS and VMOS structures for voltage and on-resistance , 1979, 1979 International Electron Devices Meeting.

[20]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[21]  Robert K. Henderson,et al.  A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology , 2010, 2010 International Electron Devices Meeting.

[22]  Anjan Chakravorty,et al.  Compact Hierarchical Bipolar Transistor Modeling With HiCUM , 2010, International Series on Advances in Solid State Electronics and Technology.

[23]  Paul G. Y. Tsui,et al.  A versatile half-micron complementary BiCMOS technology for microprocessor-based smart power applications , 1995 .

[24]  A.C.T. Aarts,et al.  Compact modeling of high-voltage LDMOS devices including quasi-saturation , 2006, IEEE Transactions on Electron Devices.

[25]  J. Kocsis,et al.  High voltage integrated circuits , 1968 .

[26]  Bantval J. Baliga,et al.  An overview of smart power technology , 1991 .

[27]  Kozo Sakamoto,et al.  A three-terminal intelligent power MOSFET with built-in reverse battery protection for automotive applications , 1999 .

[28]  M. Declercq,et al.  Avalanche breakdown in high-voltage D-MOS devices , 1976, IEEE Transactions on Electron Devices.

[29]  T. Efland,et al.  A Rugged LDMOS for LBC5 Technology , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[30]  Anjan Chakravorty,et al.  Compact modeling of SOI-LDMOS including quasi-saturation effect , 2009, 2009 2nd International Workshop on Electron Devices and Semiconductor Technology.

[31]  A.-S. Porret,et al.  A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation , 2000 .

[32]  Miss A.O. Penney (b) , 1974, The New Yale Book of Quotations.

[33]  W. Marsden I and J , 2012 .

[34]  H.G.A. Huizing,et al.  A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[35]  Weifeng Sun,et al.  A review of safe operation area , 2006, Microelectron. J..

[36]  Krishna Shenai,et al.  Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications , 1998 .

[37]  Shih Wei Sun,et al.  Integration of power LDMOS into a low-voltage 0.5 mu m BiCMOS technology , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[38]  Gerard Merckel,et al.  Triggering and sustaining of snaphack in MOSFETs , 1991, ESSDERC '91: 21st European Solid State Device Research Conference.

[39]  J. Jeong,et al.  An improvement of SOA on n-channel SOI LDMOS transistors , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[40]  P. Ratnam Novel silicon-on-insulator MOSFET for high-voltage integrated circuits , 1989 .

[41]  Chenming Hu,et al.  Internal ESD transients in input protection circuits , 1989 .

[42]  F. Krummenacher,et al.  The EPFL-EKV MOSFET Model Equations for Simulation , 1998 .