Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling

Abstract This paper introduces Approximate Error Detection-Correction (AED-C), an error management scheme suited to adaptive power management on error resilient applications. Inspired by the working principle of Approximate Computing, AED-C implements energy-accuracy scaling using the error detection coverage as a knob: a low error coverage accelerates supply voltage scaling thus to achieve larger energy savings at the cost of quality-of-result (QoR); a high error coverage lessens the voltage scaling leading to high QoR at the cost of weaker energy savings. The AED-C mechanism is built upon elastic timing monitors , Razor flip-flops augmented with a tunable detection window and hardened with the aid of a dynamic short-path padding technique. Simulations over a representative set of circuits provide a comparative analysis with the state-of-art. The collected results show AED-C substantially reduces the average energy-per-operation (up to 44.7% savings w.r.t. Razor-driven Adaptive Voltage Over-Scaling) and the area overhead (3.3% vs. 62.0%), still guaranteeing reasonable QoR. When applied to a real-life application, i.e., Forward Discrete Cosine Transform Unit (FDCT) integrated into a JPEG compressor, AED-C shows 51.9% energy savings (w.r.t. a baseline FDCT implementation) and a PSNR of 48.45 dB (w.r.t. baseline JPEG images).

[1]  K.A. Bowman,et al.  Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[2]  Jun Zhou,et al.  Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS , 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[3]  Naresh R. Shanbhag,et al.  Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[5]  Ilia Polian,et al.  Adaptive voltage over-scaling for resilient applications , 2011, 2011 Design, Automation & Test in Europe.

[6]  Massimo Alioto,et al.  Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping , 2016, VLSI-SoC.

[7]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[8]  Mingoo Seok,et al.  Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique , 2015, IEEE Journal of Solid-State Circuits.

[9]  Kaushik Roy,et al.  CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Kaushik Roy,et al.  Low-power process-variation tolerant arithmetic units using input-based elastic clocking , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[11]  Dennis Sylvester,et al.  Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails , 2014, IEEE Journal of Solid-State Circuits.

[12]  Yiorgos Tsiatouhas,et al.  Timing error tolerance in nanometer ICs , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[13]  Josep Carmona,et al.  Elastic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  David Blaauw,et al.  Razor: circuit-level correction of timing errors for low-power operation , 2004, IEEE Micro.

[15]  John Sartori,et al.  Slack redistribution for graceful degradation under voltage overscaling , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[16]  David Blaauw,et al.  Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction , 2013, IEEE Journal of Solid-State Circuits.

[17]  Xin Liu,et al.  HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[18]  Luca Benini,et al.  Battery-driven dynamic power management of portable systems , 2000, ISSS '00.

[19]  Luca Benini,et al.  Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology , 2007, GLSVLSI '07.

[20]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[21]  Enrico Macii,et al.  An automated design flow for approximate circuits based on reduced precision redundancy , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[22]  Yu-Ming Yang,et al.  PushPull: Short-Path Padding for Timing Error Resilient Circuits , 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Kaushik Roy,et al.  Voltage over-scaling: A cross-layer design perspective for energy efficient systems , 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

[24]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[25]  Enrico Macii,et al.  Temperature-Insensitive Dual- $V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Luca Benini,et al.  Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[27]  Paolo A. Aseron,et al.  A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance , 2011, IEEE Journal of Solid-State Circuits.

[28]  Shidhartha Das,et al.  A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.