An Area-Optimized Architecture for LiCi Cipher

With the rise in ubiquitous computing in resource-constrained devices, there is the huge emphasis being laid on minimal area consumption, power utilization, and optimum cost without compromising on the security objectives. Selecting lower area overhead as the target, two architectures for LiCi cipher are proposed, which primarily reduce the LUTs, slices utilized. S-boxes are one of the chief reasons for the increase in area and cost due to the memory requirements. In this chapter, we reduce the number of S-boxes, thereby reducing the overall area footprint. Based on the proposed architecture, power consumption is minimized.

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