Delay model for reconfigurable logic gates based on graphene PN-junctions

In this paper we address the problem of modeling the timing behavior of a new class of reconfigurable logic gates based on electrostatically controlled graphene pn-junctions. These gates naturally behave as a 2-to-1 multiplexer in which the polarity of the input select line can be dynamically reconfigured. Interconnection of multiple gates and proper assignments of the inputs signals allow to implement all the basic Boolean logic functions, and, at a larger scale, any digital circuit. Exploiting the symmetric structure of the graphene device, we first identify the main in-to-out timing arcs of the gate, then we derive the parametric models that accurately describe the propagation delay across them as function of the input signal transition slope and the output capacitive load. Delay equations are fit to SPICE-level simulation data by means of bilinear and linear interpolation methods; the obtained regression coefficients are stored and used as substitutes of the huge lookup-tables typically adopted in CMOS timing libraries. Experimental results show that the proposed model allows accurate timing analysis with average and peak errors below 0.6% and 3.1% respectively.