A performance-driven macro-block placer for architectural evaluation of ASIC designs

This paper presents a tool for generating a performance-driven placement from a netlist of Register-Transfer Level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks such a way that to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that our tool (1) provides solutions close to those generated manually, (2) is fast enough to be used in the inner loop of a program that synthesizes RTL structures from behavioral specifications and (3) ensures strong links between RTL synthesis and timing-driven layout so necessary for design of sub-micron ASICs.

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