Converting March tests for bit-oriented memories into tests for word-oriented memories

In this paper a set of fault models for coupling faults between the cells of a word has been established, together with tests for these fault models. Thereafter, a systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between inter-word and intra-word faults. This results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

[1]  Georgi Gaydadjiev,et al.  March LR: a test for realistic linked faults , 1996, Proceedings of 14th VLSI Test Symposium.

[2]  Ad J. van de Goor,et al.  March tests for word-oriented memories , 1998, Proceedings Design, Automation and Test in Europe.

[3]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[4]  V. K. Agarwal,et al.  Fault Location Algorithms for Repairable Embedded , 1993 .

[5]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[6]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Vinod K. Agarwal,et al.  Fault location algorithms for repairable embedded RAMs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[8]  Michael Nicolaidis,et al.  Testing complex couplings in multiport memories , 1995, IEEE Trans. Very Large Scale Integr. Syst..