A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines

A 9 Gbit/s serial link transceiver for on-chip global signaling is presented. A transmitter serializes 8 b 1.125 Gbyte/s parallel data and transmits over 5.8 mm of lossy on-chip transmission line. The receiver de-serializes the data with the help of a digitally-tuned interpolator. An error checking block verifies the recovered and de-serialized data against the original data and counts the number of discrepancies. The prototype transceiver, implemented in 0.13 mum 8 metal CMOS, achieves 9 Gbit/s with four pre-defined data patterns and a measured BER is less than 10-10.

[1]  Michael P. Flynn,et al.  Global signaling over lossy transmission lines , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[2]  M.P. Flynn,et al.  Global High-Speed Signaling in Nanometer CMOS , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[3]  M. Horowitz,et al.  Efficient on-chip global interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[4]  S. Wong,et al.  Near speed-of-light signaling over on-chip electrical interconnects , 2003 .

[5]  R. Senthinathan,et al.  A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer , 2005, IEEE Journal of Solid-State Circuits.