A high-speed two's complement multiplier using differential split-level CMOS

Abstract The design and test results of an 8 × 8 bit high-speed two's complement multiplier fabricated in a 1·5 μm n-well CMOS process are presented in this paper. The design is based on the well known modified Booth's algorithm which gives high speed at reasonably low area. Most of the cells of the multiplier are implemented in differential split-level (DSL) CMOS logic to obtain a higher multiplication speed than in conventional static CMOS. The higher static power dissipation associated with DSL CMOS can be minimized by switching the reference voltage to V DD during inactive periods while the results of the last multiplication operation remain valid. The multiplier is directly compatible with standard CMOS designs.