Practical superjunction MOSFET device performance under given process thermal cycles

The performance of specific on-state resistance (Ron,sp) versus breakdown voltage (Vbr) of a superjunction power MOSFET device is constrained by the quality of its sidewall junctions formed by neighbouring p and n columns in the drift region. The p–n junction quality, which is inevitably affected by the inter-column dopant diffusion in practice, will limit the Ron,sp–Vbr device performance if no compensation measure is taken. A detailed study of the influence of sidewall junction quality on performance at various column widths under given thermal process conditions was carried out through process and device simulations. The study discovers the practical optimal performance of superjunction (SJ) DMOS and UMOS structures under the influence of dopant inter-column diffusion. Analysis of the phenomenon shows that the degradation of the breakdown voltage is caused by the p and n column charge imbalance. Practical SJ performance equations, which model the influence reasonably well, are derived in the paper. These equations can be used to predict the practical performance of an SJ device under given thermal conditions, which in turn guides us to the compensation measures required to achieve better performance.

[1]  Steven T. Peake,et al.  Power semiconductor devices , 1995 .

[2]  S. Hine,et al.  Experimental results and simulation analysis of 250 V super trench power MOSFET (STM) , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[3]  Gary M. Dolny,et al.  Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET , 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).

[4]  Chenming Hu,et al.  Optimum doping profile for minimum ohmic resistance and high-breakdown voltage , 1979 .

[5]  J.K.O. Sin,et al.  Optimization of the specific on-resistance of the COOLMOS/sup TM/ , 2001 .

[6]  T. Fujihira.  Theory of Semiconductor Superjunction Devices , 1997 .

[7]  T. Fujihira,et al.  Simulated superior performances of semiconductor superjunction devices , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[8]  F. Morancho,et al.  A new generation of power unipolar devices: the concept of the FLoating islands MOS transistor (FLIMOST) , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[9]  Defect-less trench filling of epitaxial Si growth by H/sub 2/ annealing , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[10]  Antonio G. M. Strollo,et al.  Optimal ON-resistance versus breakdown voltage tradeoff in superjunction power devices: a novel analytical model , 2001 .

[11]  G. Deboy,et al.  COOLMOS/sup TM/-a new milestone in high voltage power MOS , 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).

[12]  D. Bensahel,et al.  Selective epitaxial silicon growth in the 650–1100 °C range in a reduced pressure chemical vapor deposition reactor using dichlorosilane , 1989 .

[13]  Xingbi Chen,et al.  New “silicon limit” of power devices , 2002 .

[14]  Xin Wang,et al.  A novel high-voltage sustaining structure with buried oppositely doped regions , 2000 .

[15]  Y.C. Liang,et al.  A simple technology for superjunction device fabrication: polyflanked VDMOSFET , 2002, IEEE Electron Device Letters.

[16]  J. Glenn,et al.  A novel vertical deep trench RESURF DMOS (VTR-DMOS) , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[17]  Florin Udrea,et al.  An analytical model for the 3D-RESURF effect , 2000 .