Programmable 50%-duty cycle frequency divider

The invention discloses a programmable 50%-duty cycle frequency divider which comprises a basic programmable frequency divider, a sampling circuit, a D (DICE (Dual Interlocked Cell)) trigger, a delay buffer chain, an odd-even decision circuit and an alternative multi-path selector. Aiming at the duty cycle problem of clock output of a programmable frequency divider during the odd frequency division of the programmable frequency divider, the basic programmable frequency divider is adopted to perform frequency division for an original clock; a clock with 50% duty cycle is output during even frequency division; a clock, the difference of a high level and a low level of which is one original clock period, is output during odd frequency division; and then, a half original clock period is respectively added to and subtracted from a high level and a lower level of the odd frequency division clock to generate an odd frequency division clock with 50% duty cycle; and thus, the programmable frequency divider can output an 50%-duty cycle clock in any frequency division ratio.