Time-Dependent Degradation in Device Characteristics and Countermeasures by Design
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Masahiko Yoshimoto | Masanori Hashimoto | Shuhei Tanakamaru | Ken Takeuchi | Takashi Sato | Jun Yao | Seiji Kajihara | Yasuo Sato | Jinwook Jung | Hiroshi Kawaguchi | Yuta Kimi | Hajime Shimada | H. Kawaguchi | S. Tanakamaru | K. Takeuchi | M. Hashimoto | M. Yoshimoto | Takashi Sato | S. Kajihara | Jinwook Jung | Jun Yao | Yasuo Sato | Hajime Shimada | Y. Kimi
[1] James H. Stathis,et al. The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..
[2] Subhasish Mitra,et al. CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns , 2008, 2008 Design, Automation and Test in Europe.
[3] John P. Hayes,et al. Online BIST for Embedded Systems , 1998, IEEE Des. Test Comput..
[4] Shuhei Tanakamaru,et al. Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming , 2012, IEEE Journal of Solid-State Circuits.
[5] Takashi Sato,et al. BTIarray: A Time-Overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability , 2014, IEEE Transactions on Device and Materials Reliability.
[6] M. Momodomi,et al. New ultra high density EPROM and flash EEPROM with NAND structure cell , 1987, 1987 International Electron Devices Meeting.
[7] Pong-Fei Lu,et al. A built-in BTI monitor for long-term data collection in IBM microprocessors , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[8] Kyungmin Kim,et al. A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[9] Seiichi Aritome. NAND Flash Innovations , 2013, IEEE Solid-State Circuits Magazine.
[10] Hong Ding,et al. A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology , 2011, 2011 IEEE International Solid-State Circuits Conference.
[11] Hiroshi Tsutsui,et al. A device array for efficient bias-temperature instability measurements , 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
[12] Kinam Kim,et al. Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[13] Shunsuke Okumura,et al. A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection , 2009, 2009 22nd International Conference on VLSI Design.
[14] Keon-Soo Kim,et al. Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays , 2009 .
[15] D. G. Pierce,et al. Electromigration: A review , 1997 .
[16] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[17] Seiji Kajihara,et al. A Stochastic Model for NBTI-Induced LSI Degradation in Field , 2013, 2013 22nd Asian Test Symposium.
[18] Ranjeet Alexis,et al. A multilevel-cell 32 Mb flash memory , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[19] Massimo Rossini,et al. A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[20] Mark Mohammad Tehranipoor,et al. A novel architecture for on-chip path delay measurement , 2009, 2009 International Test Conference.
[21] Chilhee Chung,et al. New scaling limitation of the floating gate cell in NAND Flash Memory , 2010, 2010 IEEE International Reliability Physics Symposium.
[22] Tong Zhang,et al. On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[23] Massimo Rossini,et al. A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[24] Yoon-Hee Choi,et al. Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming , 2014, IEEE Journal of Solid-State Circuits.
[25] Yo-Hwan Koh,et al. A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[26] Guido Groeseneken,et al. New insights in the relation between electron trap generation and the statistical properties of oxide breakdown , 1998 .
[27] Randy H. Katz,et al. A case for redundant arrays of inexpensive disks (RAID) , 1988, SIGMOD '88.
[28] Xiaoxiao Wang,et al. Path-RO: a novel on-chip critical path delay measurement under process variations , 2008, ICCAD 2008.
[29] Fujio Masuoka,et al. Great Encounters Leading Me to the Inventions of Flash Memories and Surrounding Gate Transistor Technology , 2013, IEEE Solid-State Circuits Magazine.
[30] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[31] Vivek De,et al. Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..
[32] Kenji Okada,et al. Extended Time Dependent Dielectric Breakdown Model Based on Anomalous Gate Area Dependence of Lifetime in Ultra Thin Silicon Dioxides , 1997 .
[33] B. Kaczer,et al. An energy-level perspective of bias temperature instability , 2008, 2008 IEEE International Reliability Physics Symposium.
[34] Jacob A. Abraham,et al. On-chip Programmable Capture for Accurate Path Delay Test and Characterization , 2008, 2008 IEEE International Test Conference.
[35] Yeong-Taek Lee,et al. A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.
[36] J. Kessenich,et al. Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.
[37] C.H. Kim,et al. Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits , 2007, 2007 IEEE Symposium on VLSI Circuits.
[38] Kiyoo Itoh,et al. Adaptive circuits for the 0.5-V nanoscale CMOS era , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[39] Tanaka,et al. A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories , 1997, Symposium 1997 on VLSI Circuits.
[40] David Blaauw,et al. Dynamic NBTI management using a 45nm multi-degradation sensor , 2010, IEEE Custom Integrated Circuits Conference 2010.
[41] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[42] S. Rauch,et al. Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.
[43] E. Vandamme,et al. Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability , 2000 .
[44] Yu Cao,et al. Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.
[45] Shianling Wu,et al. Logic BIST Architecture for System-Level Test and Diagnosis , 2009, 2009 Asian Test Symposium.
[46] Sufi Zafar. The Negative Bias Temperature Instability in MOS Devices , 2006, IIRW 2006.
[47] C. Hu. Lucky-electron model of channel hot electron emission , 1979, 1979 International Electron Devices Meeting.
[48] Asim Kadav,et al. Differential RAID: rethinking RAID for SSD reliability , 2010, OPSR.
[49] Yervant Zorian,et al. On-Line Testing for VLSI—A Compendium of Approaches , 1998, J. Electron. Test..
[50] K. Kobayashi,et al. DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test , 2012, IEEE Transactions on Nuclear Science.
[51] Toshinori Sato,et al. A Simple Flip-Flop Circuit for Typical-Case Designs for DFM , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[52] V. Rao,et al. Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs , 2000 .
[53] Motoyuki Sato,et al. DART: Dependable VLSI test architecture and its implementation , 2012, 2012 IEEE International Test Conference.
[54] Ming-Chien Tsai,et al. An All-Digital High-Precision Built-In Delay Time Measurement Circuit , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[55] Hiroaki Inoue,et al. VAST: Virtualization-Assisted Concurrent Autonomous Self-Test , 2008, 2008 IEEE International Test Conference.
[56] Sungjoo Hong,et al. Novel Negative $Vt$ Shift Phenomenon of Program–Inhibit Cell in $\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}$ Self-Aligned STI nand Flash Memory , 2012, IEEE Transactions on Electron Devices.
[57] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[58] Masanori Hashimoto,et al. Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[59] Yo-Hwan Koh,et al. A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.
[60] Alaa R. Alameldeen,et al. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation , 2008, 2008 International Symposium on Computer Architecture.
[61] William V. Huott,et al. On-chip Timing Uncertainty Measurements on IBM Microprocessors , 2008, 2008 IEEE International Test Conference.
[62] Khanh Nguyen,et al. A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[63] Yan Li,et al. A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput , 2007, IEEE Journal of Solid-State Circuits.
[64] Peter E. Cottrell,et al. Hot-electron emission in N-channel IGFET's , 1979 .
[65] Yu Cao,et al. Physics matters: Statistical aging prediction under trapping/detrapping , 2012, DAC Design Automation Conference 2012.
[66] Masanori Hashimoto,et al. Stochastic error rate estimation for adaptive speed control with field delay testing , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[67] Wonyong Sung,et al. Least squares based cell-to-cell interference cancelation technique for multi-level cell nand flash memory , 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).
[68] Ali Mohammadzadeh,et al. 19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[69] J. Black. Electromigration failure modes in aluminum metallization for semiconductor devices , 1969 .
[70] Sungwook Choi,et al. 19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[71] Young-Ho Lim,et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995 .
[72] Yan Li,et al. 128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode , 2012, 2012 IEEE International Solid-State Circuits Conference.
[73] M. Heyns,et al. Soft breakdown of ultra-thin gate oxide layers , 1996 .
[74] P. Ghate,et al. Electromigration-Induced Failures in VLSI Interconnects , 1982, 20th International Reliability Physics Symposium.
[75] Jehoshua Bruck,et al. EVENODD: An Efficient Scheme for Tolerating Double Disk Failures in RAID Architectures , 1995, IEEE Trans. Computers.
[76] A. Popa,et al. An injection level dependent theory of the MOS transistor in saturation , 1972 .
[77] Shuhei Tanakamaru,et al. Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs) , 2013, IEEE Journal of Solid-State Circuits.
[78] Paul H. Siegel,et al. Error characterization and coding schemes for flash memories , 2010, 2010 IEEE Globecom Workshops.
[79] S. Tanaka,et al. A new flash E2PROM cell using triple polysilicon technology , 1984, 1984 International Electron Devices Meeting.
[80] Matt Goldman,et al. A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[81] Yousuke Miyake,et al. Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA , 2014, 2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing.
[82] R.V. Taylor,et al. Stress Induced Voids in Aluminum Interconnects During IC Processing , 1985, 23rd International Reliability Physics Symposium.
[83] Jae-Duk Lee,et al. A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.
[84] Yukiya Miura,et al. On-chip temperature and voltage measurement for field testing , 2012, 2012 17th IEEE European Test Symposium (ETS).
[85] Krishna Parat,et al. 25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.