BoA-PTA, A Bayesian Optimization Accelerated Error-Free SPICE Solver

One of the greatest challenges in IC design is the repeated executions of computationally expensive SPICE simulations, particularly when highly complex chip testing/verification is involved. Recently, pseudo transient analysis (PTA) has shown to be one of the most promising continuation SPICE solver. However, the PTA efficiency is highly influenced by the inserted pseudo-parameters. In this work, we proposed BoA-PTA, a Bayesian optimization accelerated PTA that can substantially accelerate simulations and improve convergence performance without introducing extra errors. Furthermore, our method does not require any pre-computation data or offline training. The acceleration framework can either be implemented to speed up ongoing repeated simulations immediately or to improve new simulations of completely different circuits. BoA-PTA is equipped with cutting-edge machine learning techniques, e.g., deep learning, Gaussian process, Bayesian optimization, nonstationary monotonic transformation, and variational inference via reparameterization. We assess BoA-PTA in 43 benchmark circuits against other SOTA SPICE solvers and demonstrate an average 2.3x (maximum 3.5x) speed-up over the original CEPTA.

[1]  Andreas Krause,et al.  Information-Theoretic Regret Bounds for Gaussian Process Optimization in the Bandit Setting , 2009, IEEE Transactions on Information Theory.

[2]  M. Rezvani,et al.  Synthesis and characterization of new nanocomposite CTAB-PTA@CS as an efficient heterogeneous catalyst for oxidative desulphurization of gasoline , 2017 .

[3]  Zhangcai Huang,et al.  An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[4]  Jaijeet S. Roychowdhury,et al.  Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Bernard W. Silverman,et al.  Warping Functional Data in R and C via a Bayesian Multiresolution Approach , 2010 .

[6]  Francisco V. Fernández,et al.  An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[7]  Yasuaki Inoue,et al.  A PTA method using numerical integration algorithms with artificial damping for solving nonlinear DC circuits , 2014 .

[8]  Donald R. Jones,et al.  Efficient Global Optimization of Expensive Black-Box Functions , 1998, J. Glob. Optim..

[9]  Max Welling,et al.  Auto-Encoding Variational Bayes , 2013, ICLR.

[10]  Kwang-Ting Cheng,et al.  Electronic Design Automation: Synthesis, Verification, and Test , 2009 .

[11]  Michael M. Green,et al.  Some standard SPICE dc algorithms revisited: why does SPICE still not converge? , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[12]  Guigang Zhang,et al.  Deep Learning , 2016, Int. J. Semantic Comput..

[13]  G. Shaddick,et al.  Modeling Nonstationary Processes Through Dimension Expansion , 2010, 1011.2553.

[14]  Carl E. Rasmussen,et al.  Gaussian processes for machine learning , 2005, Adaptive computation and machine learning.

[15]  Yasuaki Inoue,et al.  Effective ramping algorithm and restart algorithm in the SPICE3 implementation for DPTA method , 2015 .

[16]  A. O'Hagan,et al.  Bayesian calibration of computer models , 2001 .

[17]  Matthew W. Hoffman,et al.  Predictive Entropy Search for Efficient Global Optimization of Black-box Functions , 2014, NIPS.

[18]  Fan Yang,et al.  Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design , 2018, ICML.

[19]  Warren B. Powell,et al.  The Correlated Knowledge Gradient for Simulation Optimization of Continuous Parameters using Gaussian Process Regression , 2011, SIAM J. Optim..

[20]  M. Günther,et al.  The DAE-index in electric circuit simulation , 1995 .

[21]  Xuan Zeng,et al.  An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[22]  Farshad Moradi,et al.  Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Ryan P. Adams,et al.  Gaussian process product models for nonparametric nonstationarity , 2008, ICML '08.

[24]  A.A. Shah,et al.  Manifold learning for the emulation of spatial fields from computational models , 2016, J. Comput. Phys..

[25]  Huazhong Yang,et al.  Parallel Sparse Direct Solver for Integrated Circuit Simulation , 2017 .

[26]  J. Mockus Bayesian Approach to Global Optimization: Theory and Applications , 1989 .

[27]  Michalis K. Titsias,et al.  Variational Learning of Inducing Variables in Sparse Gaussian Processes , 2009, AISTATS.

[28]  Zi Wang,et al.  Max-value Entropy Search for Efficient Bayesian Optimization , 2017, ICML.

[29]  Jan Ogrodzki,et al.  DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors , 2012 .

[30]  ter Ejw Jan Maten,et al.  Robust time-domain source stepping for DC-solution of circuit equations , 2012 .

[31]  Brucek Khailany,et al.  High Performance Graph ConvolutionaI Networks with Applications in Testability Analysis , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[32]  Xuan Zeng,et al.  An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

[33]  Andrew Gordon Wilson,et al.  Deep Kernel Learning , 2015, AISTATS.

[34]  Yasuaki Inoue,et al.  An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Kaushik Roy,et al.  Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis , 2002, Proceedings. International Test Conference.

[36]  Xuan Zeng,et al.  Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[37]  J. A. Barby,et al.  CircuitSim93: A circuit simulator benchmarking methodology case study , 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.

[38]  Yu Wang,et al.  Machine Learning for Electronic Design Automation: A Survey , 2021, ACM Trans. Design Autom. Electr. Syst..