Innovative approaches for realisation of embedded chip packages - Technological challenges and achievements

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components. Among its merits, it provides superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment for the chips and thus resulting in superior reliability. At PCB manufacturing level, 50 µm thin chips have been embedded with pitches up to 200 µm in up to 18″×24″ panels. This paper shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400µm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100µm pitch. All Embedded chip-QFN packages have been manufactured in 10″×14″ panels at prototype level. This paper explains in detail all process steps and technical challenges encountered for the QFN package manufacturing. The final packaging routing necessitates challenging technology developments in ultra fine line patterning. The paper shows the successful employment of laser-direct-imaging technology in semi-additive-processes for the creation of very fine 18µm copper lines with 10µm spaces between them. Very thin 2µm Copper foils were used for this study as a plating base and for the final Copper flash etching during semi-additive-process. These important technological developments have been achieved with advancements in laser direct imaging technique of negative photoresist films which allows the whole patterning to be done without use of expensive masks. Additionally, it cuts off processing time and it can yield very dense copper patterning up to the technological limit of the LDI technique. The paper also elaborates on embedding strategies for chips with contact pitches even smaller than 100µm either with vialess methods to contact pads or by flip chip interconnection and then chip embedding. This study shows promising results for embedding of chips with different contact pitches through alternative embedding strategies and in conjunction with developments for very dense copper routing, it provides strong evidence for the manufacturability of highly miniaturised embedded chip system-in-packages.