A novel design of wafer yield model for semiconductor using a GMDH polynomial and principal component analysis

[1]  Karl Pearson F.R.S..  LIII. On lines and planes of closest fit to systems of points in space , 1901 .

[2]  A. G. Ivakhnenko,et al.  Polynomial Theory of Complex Systems , 1971, IEEE Trans. Syst. Man Cybern..

[3]  C. Stapper.  Defect density distribution for LSI yield calculations , 1973 .

[4]  J. A. Cunningham.  The use and evaluation of yield models in integrated circuit manufacturing , 1990 .

[5]  Susan L. Albin,et al.  Clustered defects in IC fabrication: Impact on process control charts , 1991 .

[6]  C. H. Stapper,et al.  On Murphy's yield integral (IC manufacture) , 1991 .

[7]  M. A. Bayoumi,et al.  Defect clustering viewed through generalized Poisson distribution , 1992 .

[8]  R.C. Leachman.  The Competitive Semiconductor Manufacturing Survey , 1993, International Symposium on Semiconductor Manufacturing.

[9]  M. A. Bayoumi,et al.  The nature of defect patterns on integrated-circuit wafer maps , 1994 .

[10]  C. H. Stapper,et al.  Integrated circuit yield management and yield analysis: development and implementation" ieee trans , 1995 .

[11]  Vijayan N. Nair,et al.  Model-free estimation of defect clustering in integrated circuit fabrication , 1997 .

[12]  Chao-Ton Su,et al.  Using a neural network-based approach to predict the wafer yield in integrated circuit manufacturing , 1997 .

[13]  Chi-Hyuck Jun,et al.  A simulation-based semiconductor chip yield model incorporating a new defect cluster index , 1999 .

[14]  R. E. Langford,et al.  The application and validation of a new robust windowing method for the Poisson yield model , 2001, 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (IEEE Cat. No.01CH37160).

[15]  Juin J. Liou,et al.  Statistical Modeling of MOS Devices for Parametric Yield Prediction , 2002 .

[16]  F. Lemke,et al.  Self-Organising Data Mining , 2003 .

[17]  Nohpill Park,et al.  Predicting Defect-Tolerant Yield in the Embedded Core Context , 2003, IEEE Trans. Computers.

[18]  R. Kielbasa,et al.  Modeling semiconductor manufacturing yield by test data and partial least squares , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[19]  D. Baldwin,et al.  A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification , 2005, IEEE Transactions on Electronics Packaging Manufacturing.

[20]  Douglas C. Montgomery,et al.  A review of yield modelling techniques for semiconductor manufacturing , 2006 .

[21]  Lee-Ing Tong,et al.  Development of a new cluster index for wafer defects , 2006 .

[22]  Lee-Ing Tong,et al.  Novel yield model for integrated circuits with clustered defects , 2008, Expert Syst. Appl..

[23]  Ian T. Jolliffe,et al.  Principal Component Analysis , 2002, International Encyclopedia of Statistical Science.