Using Data Contention in Dual-ported Memories for Security Applications

Field Programmable Gate Arrays (FPGA) provide the invaluable feature of dynamic hardware reconfiguration by loading configuration bit files. However, this flexibility also opens up the threat of theft of Intellectual Property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind an application configuration to a specific device is an important step to prevent product counterfeiting. Furthermore, such a technology can also enable advanced business models such as device-specific feature activation. In this work, we present a new technique to generate entropy on FPGA device—based on data contention in the hardware circuitry. For this entropy, we use the output of intentionally generated write collisions in synchronous dual-ported block RAMs (BRAM). We show that the parts of this output generated by such write collisions can be either probabilistic but also deterministic and device-specific. The characteristics of such an entropy source can be used for a large variety of security applications, such as chip identification and device authentication. In addition to that, we also propose a solution to efficiently create cryptographic keys on-chip at runtime. As a last contribution, we eventually present a strategy how to transform this entropy source into a circuit for True Random Number Generation (TRNG).

[1]  Tim Güneysu,et al.  Dynamic Intellectual Property Protection for Reconfigurable Devices , 2007, 2007 International Conference on Field-Programmable Technology.

[2]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[3]  J. Rice Mathematical Statistics and Data Analysis , 1988 .

[4]  Werner Schindler,et al.  Efficient Online Tests for True Random Number Generators , 2001, CHES.

[5]  S. Walker,et al.  Evaluating metastability in electronic circuits for random number generation , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[6]  Jovan Dj. Golic,et al.  High-Speed True Random Number Generation with Logic Gates Only , 2007, CHES.

[7]  Christof Paar,et al.  Cryptographic Hardware and Embedded Systems - CHES 2002 , 2003, Lecture Notes in Computer Science.

[8]  Mitsuru Matsui,et al.  Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings , 2006, CHES.

[9]  Tim Güneysu,et al.  Transforming write collisions in block RAMs into security applications , 2009, 2009 International Conference on Field-Programmable Technology.

[10]  Rafail Ostrovsky,et al.  Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data , 2004, SIAM J. Comput..

[11]  Kris Gaj,et al.  An embedded true random number generator for FPGAs , 2004, FPGA '04.

[12]  G.-J. Schrijen,et al.  Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[13]  Christof Paar,et al.  Cryptographic Hardware and Embedded Systems - CHES 2003 , 2003, Lecture Notes in Computer Science.

[14]  J.D. Golic,et al.  New Methods for Digital Generation and Postprocessing of Random Data , 2006, IEEE Transactions on Computers.

[15]  Hao Zheng,et al.  Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts , 2003, CHES.

[16]  Ingrid Verbauwhede,et al.  Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings , 2007, CHES.

[17]  Sergio Callegari,et al.  First direct implementation of a true random source on programmable hardware , 2005, Int. J. Circuit Theory Appl..

[18]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[19]  Tom Kean,et al.  Cryptographic rights management of FPGA intellectual property cores , 2002, FPGA '02.

[20]  J.-L. Danger,et al.  High speed true random number generator based on open loop structures in FPGAs , 2009, Microelectron. J..

[21]  Philip Heng Wai Leong,et al.  Compact FPGA-based true and pseudo random number generators , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[22]  Sergio Callegari,et al.  First direct implementation of a true random source on programmable hardware: Research Articles , 2005 .

[23]  E.Y. Lam,et al.  FPGA-based High-speed True Random Number Generator for Cryptographic Applications , 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

[24]  David Naccache,et al.  Cryptographic Hardware and Embedded Systems — CHES 2001 , 2001 .

[25]  Maureen Smerdon Security Solutions Using Spartan-3 Generation FPGAs , 2008 .

[26]  Boris Skoric,et al.  Read-Proof Hardware from Protective Coatings , 2006, CHES.

[27]  John Kelsey,et al.  Recommendation for Random Number Generation Using Deterministic Random Bit Generators , 2014 .

[28]  Elisabeth Oswald,et al.  Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings , 2008, CHES.

[29]  Ahmad-Reza Sadeghi,et al.  Efficient Helper Data Key Extractor on FPGAs , 2008, CHES.

[30]  Jorge Guajardo,et al.  Extended abstract: The butterfly PUF protecting IP on every FPGA , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[31]  Werner Schindler,et al.  Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications , 2002, CHES.

[32]  Patrick Schaumont,et al.  Offline Hardware/Software Authentication for Reconfigurable Platforms , 2006, CHES.

[33]  Milos Drutarovský,et al.  True Random Number Generator Embedded in Reconfigurable Hardware , 2002, CHES.

[34]  Tim Güneysu,et al.  Cryptanalysis with COPACOBANA , 2008, IEEE Transactions on Computers.

[35]  Stephen A. Benton,et al.  Physical one-way functions , 2001 .

[36]  Berk Sunar,et al.  A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks , 2007, IEEE Transactions on Computers.

[37]  Ingrid Verbauwhede,et al.  Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs , 2009, CHES.