Exploiting transaction level models for observability-aware post-silicon test generation

A major challenge in post-silicon debug is to generate efficient tests that activate requisite coverage goals on the target hardware while also producing results that are observable through a given on-chip design-for-debug (DfD) architecture. Unfortunately, such tests cannot be generated by analysis of RTL models, both because of design complexity and since the implementation can be buggy. In this paper, we propose an approach to address this problem by exploiting transaction-level models (TLM). Our approach involves mapping tests and observability requirements between TLM and RTL, enabling TLM analysis to generate post-silicon tests. We provide two case studies to demonstrate the flexibility and effectiveness of our proposed approach.