FPGA Implementation of PICO Cipher

The rise in ubiquitous computing connecting resource-constrained devices had led to the emergence of a sub-domain in cryptography called lightweight cryptography. The algorithms in this domain target moderate security while satisfying the constraints set for a desired application. PICO is one of the lightweight SPN ciphers suitable for low-area and low-power applications. In this paper, two hardware architectures ideal for low-area footprint and low power are proposed. This comprises a serial architecture and a reduced datapath architecture which are designed specifically for reduced area and low-power applications while choosing trade-offs from latency and performance. The results are evaluated for Xilinx FPGA platforms like Spartan 3, Virtex 4 and Virtex 6. The synthesis and implementation of the proposed architectures are performed using Verilog HDL in Xilinx ISE Design Suite 14.6. The area footprint is estimated in terms of the slices, flip flops and LUTs. The power consumption is estimated using XPower Analyzer for a clock frequency of 10 MHz. The simulations for the proposed designs are verified using ISim Simulator. Further, the area in terms of slices occupied is compared with the existing ciphers for Spartan 3 and Virtex 4 families.