Defect-Oriented Testing of RF Circuits

Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric defects as deviations in physical circuit parameters, such as resistances, transistor widths, and lengths, and inject open- and short-circuit defects into the critical locations that are derived from the layout using inductive fault analysis. Despite fault injection, we consider a circuit unacceptable only if it violates any one of the performance specifications. Our test development method aims at reducing not only the number of measurements but also the overall test hardware cost by incorporating the relative setup cost of each measurement into our selection criteria. Experimental results on an RF front-end device show that our test methodology reduces the test time by 50% and the number of test setups by 17% while identifying all unacceptable circuit instances with a 99% failure coverage without any yield loss.

[1]  Edward J. McCluskey,et al.  Testing for tunneling opens , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[2]  Mustapha Slamani,et al.  A low-cost test solution for wireless phone RFICs , 2003, IEEE Commun. Mag..

[3]  Karthik Sundararaman.  Design For Manufacturability - Fault Model Extensions for RF Circuits with Economic Perspective for Manufacturability , 2004 .

[4]  Abhijit Chatterjee,et al.  MIXER: Mixed-signal fault simulator , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[5]  Linda S. Milor,et al.  Detection of catastrophic faults in analog integrated circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  M.L. Liou,et al.  Computer-aided analysis of electronic circuits: Algorithms and computational techniques , 1977, Proceedings of the IEEE.

[7]  André Ivanov,et al.  Fault simulation and testing of an OTA biquadratic filter , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[8]  Bozena Kaminska,et al.  Analog circuit testing based on sensitivity computation and new circuit modeling , 1993, Proceedings of IEEE International Test Conference - (ITC).

[9]  Soon-Jyh Chang,et al.  Structural Fault Based Specification Reduction for Testing Analog Circuits , 2002, J. Electron. Test..

[10]  Abhijit Chatterjee,et al.  Automatic multitone alternate test-generaton for rf circuits using behavioral models , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.

[12]  Sule Ozev,et al.  Diagnosis of the failing component in RF receivers through adaptive full-path measurements , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[13]  Wojciech Maly,et al.  Extracting Defect Density and Size Distributions from Product ICs , 2006, IEEE Design & Test of Computers.

[14]  Stephen K. Sunter,et al.  Test metrics for analog parametric faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[15]  Charles F. Hawkins,et al.  IDDQ testing: A review , 1992, J. Electron. Test..

[16]  Charles F. Hawkins,et al.  THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[17]  Florence Azaïs,et al.  Improving Defect Detection in Static-Voltage Testing , 2002, IEEE Des. Test Comput..

[18]  Ronald S. Gyurcsik,et al.  Optimal ordering of analog integrated circuit tests to minimize test time , 1991, 28th ACM/IEEE Design Automation Conference.

[19]  T. Yamaguchi,et al.  Integrated electrical and SEM defect characterization for rapid yield ramp , 2003 .

[20]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[21]  M. Soma,et al.  Challenges in analog and mixed-signal fault models , 1996 .

[22]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[23]  Rob A. Rutenbar,et al.  A Tutorial Introduction to Research on Analog and MixedSignal Circuit Testing , 2002 .

[24]  Sule Ozev,et al.  Delayed-RF based test development for FM transceivers using signature analysis , 2004, 2004 International Conferce on Test.

[25]  Mani Soma,et al.  An experimental approach to analog fault models , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[26]  Jennifer Salin Miller.  ANALYTICAL EVALUATION OF PERFORMANCE VARIABILITY IN DIGITAL CIRCUITS DUE TO PROCESS VARIABILITY , 2005 .

[27]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[28]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  John Paul Shen,et al.  A CMOS fault extractor for inductive fault analysis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Bozena Kaminska,et al.  Multifrequency Analysis of Faults in Analog Circuits , 1995, IEEE Des. Test Comput..

[31]  J. Dabrowski.  Fault modeling of RF blocks based on noise analysis , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[32]  F. Joel Ferguson,et al.  Carafe: an inductive fault analysis tool for CMOS VLSI circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[33]  Manoj Sachdev,et al.  Defect-oriented test methodology for complex mixed-signal circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[34]  Bozena Kaminska,et al.  Closing the gap between analog and digital testing , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Marcel Jacomet,et al.  Layout-dependent fault analysis and test synthesis for CMOS circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Kurt Antreich,et al.  Design based analog testing by Characteristic Observation Inference , 1995, ICCAD.

[37]  André Ivanov,et al.  An all-digital DFT scheme for testing catastrophic faults in PLLs , 2003, IEEE Design & Test of Computers.

[38]  João Paulo Teixeira,et al.  Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[39]  Manoj Sachdev,et al.  Industrial relevance of analog IFA: a fact or a fiction , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[40]  A. Sangiovanni-Vincentelli,et al.  Optimal test set design for analog circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.