A 2.2 GHz Continuous-Time $\mathrm {\Delta \!\Sigma }$ ADC With −102 dBc THD and 25 MHz Bandwidth

This paper presents a 2.2 GHz continuous-time AΣ ADC that achieves -102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are -115 dBc and -114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.

[1]  James C. Candy,et al.  A Use of Double Integration in Sigma Delta Modulation , 1985, IEEE Trans. Commun..

[2]  Kofi A. A. Makinwa,et al.  A 4 GHz Continuous-Time ΔΣ ADC , 2014 .

[3]  Michael P. Flynn,et al.  A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Robert H. M. van Veldhoven,et al.  An Inverter-Based Hybrid ΔΣ Modulator , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Johan H. Huijsing,et al.  Operational Amplifiers - Theory and Design , 2000 .

[7]  Bram Nauta,et al.  A CMOS transconductance-C filter technique for very high frequencies , 1992 .

[8]  Philippe Bénabès,et al.  A methodology for designing continuous-time sigma-delta modulators , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[9]  Shanthi Pavan,et al.  Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.

[10]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR , 2008, IEEE Journal of Solid-State Circuits.

[11]  Boris Murmann,et al.  A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[12]  D.A. Mercer,et al.  Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-$\mu$m CMOS , 2007, IEEE Journal of Solid-State Circuits.

[13]  Hajime Shibata,et al.  Advances in high-speed continuous-time delta-sigma modulators , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[14]  Quan Pan,et al.  A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Michael P. Flynn,et al.  A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF , 2014, IEEE Journal of Solid-State Circuits.

[16]  Martin Posch,et al.  Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[17]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[18]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[19]  Thomas Christen.  A 15-bit 140-$\mu$ W Scalable-Bandwidth Inverter-Based $\Delta \Sigma $ Modulator for a MEMS Microphone With Digital Output , 2013, IEEE Journal of Solid-State Circuits.

[20]  M. Bolatkale,et al.  A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$74 dBFS THD in 125 MHz BW , 2011, IEEE Journal of Solid-State Circuits.

[21]  Cong Liu,et al.  A 4.5 mW CT Self-Coupled $\Delta\Sigma$ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation , 2015, IEEE Journal of Solid-State Circuits.

[22]  Cong Liu,et al.  15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[23]  L. Schuchman.  Dither Signals and Their Effect on Quantization Noise , 1964 .

[24]  Robert W. Adams,et al.  Design and Implementation of an Audio 18-Bit Analog-to-Digital Converter Using Oversampling Techniques , 1986 .

[25]  Joerg Wenzel,et al.  A wideband single-PLL RF receiver for simultaneous multi-band and multi-channel digital car Radio reception , 2016, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[26]  Akira Matsuzawa,et al.  A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator , 2010, IEEE Journal of Solid-State Circuits.

[27]  Robert Weigel,et al.  A 9th-order continuous time ΣΔ-ADC with x-coupled differential single-opamp resonators , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[28]  Pietro Andreani,et al.  A Filtering ΔΣ ADC for LTE and Beyond , 2014, IEEE Journal of Solid-State Circuits.

[29]  Kong-Pang Pun,et al.  A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC , 2007, IEEE Journal of Solid-State Circuits.

[30]  Robert H. M. van Veldhoven,et al.  A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.