An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits

A new method is presented which allows us to optimize active device area in complex mismatch- and 1/f-noise-sensitive analog integrated circuits. The method is based on a fully analytical approach and represents an efficient alternative to time consuming Monte-Carlo simulations and numerical iteration procedures. Moreover, it allows us to estimate total chip areas required to guarantee matching and noise performance with a high precision. The method is suitable for integration in the design flow of mixed signal circuits.

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