Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies

Spin transfer torque based magnetic memories (STT-MRAMs) are leading contender for the replacement of SRAM caches. However, STT-MRAMs suffer from high write current, read/write stability conflicts and other failure mechanisms. In this paper, we present a comprehensive scaling analysis for STT-MRAMs based on in-plane and perpendicular anisotropy magnets in context to different failure mechanisms. Write failures are taken into consideration by the write current, read disturb failures by the critical current and read decision failure by the tunnel magneto-resistance scaling trends. Bit-cells comprising three different device structures-the conventional magnetic tunnel junctions (MTJs), the dual pillar MTJs (DP-MTJs) and the spin-orbit-torque based MTJs (SOT-MTJs) are investigated. We analyze the robustness of the aforementioned devices within the voltage constraints specified by ITRS. We also report predictive analysis results with futuristic material parameters. Through a coupled simulation framework consisting of spin transport and magnetization dynamics, we show that conventional MTJs would require higher voltages at scaled technology nodes. DP-MTJs, within ITRS voltage specifications, show better scalability (with ~ 2.3× larger bit-cell area). SOT-MTJs provide attractive power savings ( ~ 3.4× improvement) at a ~ 1.3× larger bit-cell area. Furthermore, our analysis indicates that among various possible improved material parameters, high interface perpendicular anisotropy shows the most promising way of achieving scalable memory cells at assumed ITRS voltages.

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