A low-cost single-event latchup mitigation scheme
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[1] H.P. Zappe,et al. A transient analysis of latchup in bulk CMOS , 1983, IEEE Transactions on Electron Devices.
[2] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[3] J. F. Leavy,et al. Radiation-Induced Integrated Circuit Latchup , 1969 .
[4] Christos A. Papachristou,et al. An efficient BICS design for SEUs detection and correction in semiconductor memories , 2005, Design, Automation and Test in Europe.
[5] T. Calin,et al. A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results , 1995 .
[6] Ronald R. Troutman,et al. Latchup in CMOS Technology: The Problem and Its Cure , 1986 .
[7] Paul E. Dodd,et al. Neutron-induced latchup in SRAMs at ground level , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[8] G. Bruguier,et al. Single particle-induced latchup , 1996 .
[9] A. Ochoa,et al. An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process , 1978, 1978 International Electron Devices Meeting.
[10] Mark C. Johnson,et al. Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[11] Ronald R. Troutman. Latchup in CMOS Technology , 1986 .
[12] P.E. Dodd,et al. Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies , 2002, Digest. International Electron Devices Meeting,.
[13] Michael Nicolaidis,et al. SEU-tolerant SRAM design based on current monitoring , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.
[14] R. Troutman,et al. Epitaxial layer enhancement of n-well guard rings for CMOS circuits , 1983, IEEE Electron Device Letters.