Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing

In this tutorial, we present a comprehensive approach to non-intrusive monitoring of multi-core processors. Modern multi-core processors come with trace-ports that provide a highly compressed trace of the instructions executed by the processor. We describe how these compressed traces can be used to reconstruct the actual control flow trace executed by the program running on the processor and to carry out analyses on the control flow trace in real time using FPGAs. We further give an introduction to the temporal stream-based specification language TeSSLa and show how it can be used to specify typical constraints of a cyber-physical system from the railway domain. Finally, we describe how light-weight, hardware-supported instrumentation can be used to enrich the control-flow trace with data values from the application.

[1]  Dejan Nickovic,et al.  Runtime Monitoring with Recovery of the SENT Communication Protocol , 2017, CAV.

[2]  Matthias Függer,et al.  Runtime verification of embedded real-time systems , 2014, Formal Methods Syst. Des..

[3]  Martin Leucker,et al.  Teaching Runtime Verification , 2011, RV.

[4]  Martin Leucker,et al.  TeSSLa: Temporal Stream-based Specification Language , 2018, SBMF.

[5]  Gary J. Nutt,et al.  Tutorial: Computer System Monitors , 1975, Computer.

[6]  Martin Leucker,et al.  Runtime verification for multicore SoC with high-quality trace data , 2013, TODE.

[7]  Martin Leucker,et al.  A brief account of runtime verification , 2009, J. Log. Algebraic Methods Program..

[8]  Lennart Lindh,et al.  A hardware and software monitor for high-level system-on-chip verification , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[9]  Jeffrey J. P. Tsai,et al.  A Noninterference Monitoring and Replay Mechanism for Real-Time Software Testing and Debugging , 1990, IEEE Trans. Software Eng..

[10]  Johann Schumann,et al.  R2U2: monitoring and diagnosis of security threats for unmanned aerial systems , 2017, RV.

[11]  Dejan Nickovic,et al.  From signal temporal logic to FPGA monitors , 2015, 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE).

[12]  Hong Lu,et al.  Automatic Processor Customization for Zero-Overhead Online Software Verification , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Bernd Finkbeiner,et al.  LOLA: runtime monitoring of synchronous systems , 2005, 12th International Symposium on Temporal Representation and Reasoning (TIME'05).

[14]  Bernd Finkbeiner,et al.  A Stream-Based Specification Language for Network Monitoring , 2016, RV.

[15]  Dejan Nickovic,et al.  Quantitative monitoring of STL with edit distance , 2016, Formal Methods in System Design.

[16]  Sebastian Fischmeister,et al.  Non-intrusive Runtime Monitoring Through Power Consumption: A Signals and System Analysis Approach to Reconstruct the Trace , 2016, RV.

[17]  Martin Leucker,et al.  Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems , 2017, SBMF.

[18]  Grigore Rosu,et al.  Hardware Runtime Monitoring for Dependable COTS-Based Real-Time Embedded Systems , 2008, 2008 Real-Time Systems Symposium.

[19]  Julien DeAntoni,et al.  Tool Support for the Analysis of TADL2 Timing Constraints Using TimeSquare , 2013, 2013 18th International Conference on Engineering of Complex Computer Systems.