On runtime management in multi-core packet processing systems

Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing systems on routers employ multiple processor cores. We investigate the design of an efficient run-time management system that handles the allocation of processing tasks to processor cores. Using run-time profiling information about processing requirements and traffic characteristics, the system is able to adapt to dynamic changes in the workload and balance the utilization of all processing resources to maximize throughput. We present a prototype implementation of our system that is based on the Click modular router. Our results show that our prototype system can adapt to changing workloads and process computationally demanding packets at 1.32 times higher data rates than SMP Click.

[1]  Harrick M. Vin,et al.  A case for run-time adaptation in packet processing systems , 2004, Comput. Commun. Rev..

[2]  Bernhard Plattner,et al.  Router Plugins: A Modular and Extensible Software Framework for Modern High Performance Integrated Services Routers , 1998 .

[3]  Jonathan S. Turner.  A proposed architecture for the GENI backbone platform , 2006, 2006 Symposium on Architecture For Networking And Communications Systems.

[4]  Eddie Kohler,et al.  The Click modular router , 1999, SOSP.

[5]  David Wetherall,et al.  Towards an active network architecture , 1996, CCRV.

[6]  Fred Kuhns,et al.  Supercharging planetlab: a high performance, multi-application, overlay network platform , 2007, SIGCOMM '07.

[7]  Scott Shenker,et al.  Overcoming the Internet impasse through virtualization , 2005, Computer.

[8]  Tilman Wolf,et al.  Runtime Support for Multicore Packet Processing Systems , 2007, IEEE Network.

[9]  Bernhard Plattner,et al.  Router plugins: a software architecture for next generation routers , 1998, SIGCOMM '98.

[10]  Larry L. Peterson,et al.  The x-Kernel: An Architecture for Implementing Network Protocols , 1991, IEEE Trans. Software Eng..

[11]  Glen Gibb,et al.  NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[12]  K. Keutzer,et al.  Automated Task Allocation for Network Processors , 2004 .

[13]  Tilman Wolf,et al.  Design of a Network Service Architecture , 2007, 2007 16th International Conference on Computer Communications and Networks.

[14]  Jonathan M. Smith,et al.  On-the-fly programmable hardware for networks , 1998, IEEE GLOBECOM 1998 (Cat. NO. 98CH36250).

[15]  Greg Grohoski.  Niagara-2: A highly threaded server-on-a-chip , 2006, 2006 IEEE Hot Chips 18 Symposium (HCS).

[16]  Anja Feldmann,et al.  Internet clean-slate design: what and why? , 2007, CCRV.

[17]  Yu Zhang,et al.  Automated task distribution in multicore network processors using statistical analysis , 2007, ANCS '07.

[18]  Robert Tappan Morris,et al.  Flexible Control of Parallelism in a Multiprocessor PC Router , 2001, USENIX Annual Technical Conference, General Track.

[19]  Yitzchak M. Gottlieb,et al.  Building a robust software-based router using network processors , 2001, SOSP.

[20]  Kenneth L. Calvert,et al.  Lightweight network support for scalable end-to-end services , 2002, SIGCOMM '02.

[21]  Kurt Keutzer,et al.  NP-Click: a productive software development approach for network processors , 2004, IEEE Micro.

[22]  Stephen D. Goglin.  Advanced Software Framework , Tools , and Languages for the IXP Family , 2003 .