A high-performance 0.25- mu m CMOS technology. I. Design and characterization

A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >

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