Methodologies for high-level modelling and evaluation in the automotive domain

As design complexity increases, todaypsilas HDL-based design flows push the capabilities of designers and tools to the limit. In recent years, ambitious efforts at increasing the abstraction level of formal design languages have been presented in order to overcome these limitations. Nevertheless, certain parts of all systems still have to be described in detail. Unfortunately, even small analog parts can slow down a global system simulation significantly. It is therefore necessary to generate abstract models with reduced but adequate result accuracy for these ldquobottleneckrdquo components. This paper presents a novel approach to the automated generation and evaluation of abstract behavioural models for automotive applications. Our methodology aims at achieving a convincing speedup in global system verification by accelerating the transient simulation of the crucial analog and mixed-signal components. The speedup results not only from an increased level of abstraction but also from a fast generation of circuit equations without the need for numerical integration. The approach is able to handle nonlinear circuits by employing piecewise linear models. The use of a SystemC interface will allow effortless integration into manifold simulation environments.

[1]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[2]  Christoph Grimm,et al.  Extending SystemC to support mixed discrete-continuous system modeling and simulation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  J. A. MARTINEZ,et al.  Mixed-Technology System-Level Simulation , 2001 .

[4]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[5]  S. Natarajan,et al.  A systematic method for obtaining state equations using MNA , 1991 .

[6]  Domine M. W. Leenaerts,et al.  Piecewise Linear Modeling and Analysis , 1998 .

[7]  Stuart Swan,et al.  SystemC transaction level models and RTL verification , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[8]  Xin Li,et al.  Behavioral modeling for analog system-level simulation by wavelet collocation method , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[9]  Christoph Grimm,et al.  A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[10]  Albert E. Ruehli,et al.  The modified nodal approach to network analysis , 1975 .

[11]  Lars Hedrich,et al.  Hierarchical automatic behavioral model generation of nonlinear analog circuits based on nonlinear symbolic techniques , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[12]  Daniel Gajski,et al.  RTL semantics and methodology , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[13]  Jean-Marc Daveau,et al.  Automating the Design of SOCs Using Cores , 2001, IEEE Des. Test Comput..

[14]  S. Haley,et al.  The generalized eigenproblem: pole-zero computation , 1988, Proceedings of the IEEE.