Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs

In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.

[1]  B.L. Bhuva,et al.  RHBD techniques for mitigating effects of single-event hits using guard-gates , 2005, IEEE Transactions on Nuclear Science.

[2]  S. Whitaker,et al.  Low power SEU immune CMOS memory circuits , 1992 .

[3]  Hideki Oka,et al.  An Accurate and Comprehensive Soft Error Simulator NISES II , 2004 .

[4]  J. Canaris,et al.  SEU hardened memory cells for a CCSDS Reed-Solomon encoder , 1991 .

[5]  S. Matsuda,et al.  Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity , 2005, IEEE Transactions on Nuclear Science.

[6]  T. May,et al.  Alpha-particle-induced soft errors in dynamic memories , 1979, IEEE Transactions on Electron Devices.

[7]  M. Yokokawa Present status of development of the Earth Simulator , 2001, 2001 Innovative Architecture for Future Generation High-Performance Processors and Systems.

[8]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[9]  Naresh R. Shanbhag,et al.  Sequential Element Design With Built-In Soft Error Resilience , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[11]  Taiki Uemura,et al.  Neutron-induced Soft-Error Simulation Technology for Logic Circuits , 2005 .

[12]  Yoshiharu Tosaka,et al.  Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits , 1998 .

[13]  P.H. Eaton,et al.  SEU and SET Modeling and Mitigation in Deep Submicron Technologies , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[14]  Jr. Leonard R. Rockett An SEU-hardened CMOS data latch design , 1988 .

[15]  R. Baumann Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[16]  M. Igeta,et al.  Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[17]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[18]  Hideo Ito,et al.  Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[19]  R. Velazco,et al.  Design of SEU-hardened CMOS memory cells: the HIT cell , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[20]  Ming Zhang,et al.  A CMOS design style for logic circuit hardening , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[21]  James F. Ziegler,et al.  Terrestrial cosmic rays , 1996, IBM J. Res. Dev..