Hot-Spot Traffic Pattern on Hierarchical 3D Mesh Network

A Hierarchical 3D-Mesh (H3DM) Network is a 2D-mesh network of multiple basic modules (BMs), in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. In this paper, we evaluate the dynamic communication performance of a H3DM network under hot-spot traffic pattern using a deadlock-free dimension order routing algorithm with minimum number of virtual channels. We have also evaluated the dynamic communication performance of the mesh and torus networks. It is shown that under most imbalance hot-spot traffic pattern H3DM network yields high throughput and low average transfer time than that of mesh and torus networks, providing better dynamic communication performance compared to those networks.

[1]  Massoud Pedram,et al.  A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution , 2009, J. Low Power Electron..

[2]  Ramón Beivide,et al.  L-Networks: A Topological Model for Regular 2D Interconnection Networks , 2013, IEEE Transactions on Computers.

[3]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[4]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[5]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[6]  Laxmikant V. Kalé,et al.  Avoiding hot-spots on two-level direct networks , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[7]  Jun Yang,et al.  Simple virtual channel allocation for high throughput and high frequency on-chip routers , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[8]  Shashi Kumar,et al.  HiRA: A methodology for deadlock free routing in hierarchical networks on chip , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[9]  Yi Pan,et al.  Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model , 2009, IEEE Transactions on Computers.

[10]  Asadullah Shah,et al.  On Dynamic Communication Performance of a Hierarchical 3D-Mesh Network , 2012, NPC.

[11]  Jian Wang,et al.  System-level Buffer Allocation for Application Specific Network-on-chip with Wormhole Routing , 2012 .

[12]  Pao-Lien Lai,et al.  A class of hierarchical graphs as topologies for interconnection networks , 2010, Theor. Comput. Sci..

[13]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[14]  Gregory F. Pfister,et al.  “Hot spot” contention and combining in multistage interconnection networks , 1985, IEEE Transactions on Computers.

[15]  Jungang Han,et al.  RTTM: A New Hierarchical Interconnection Network for Massively Parallel Computing , 2009, HPCA.

[16]  Y. Inoguchi,et al.  A deadlock-free dimension order routing for hierarchical 3D-Mesh network , 2012, 2012 International Conference on Computer & Information Science (ICCIS).

[17]  Turki F. Al-Somani,et al.  Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison , 2011, J. Electr. Comput. Eng..