Nondestructive Multilevel Interconnect Parameter Characterization For High-performance Manufacturable VLSI Technologies

One of the challenges in VLSI fabrication is to design submicron multilevel metals with high yield. This paper describes a concurrent engineering methodology that provides semiconductor engineers and VLSI circuit designers with an efficient test, modeling, and SPICE-level simulation environment. At the beginning of interconnect technology selection/evaluation, comprehensive and representative 3-D interconnect test structures are designed and fabricated for each technology option. The geometric parameters and their standard deviations are then characterized by measured data using 3-D-simulated ‘thickness vs. capacitance’ curves. A spreadsheet-based Universal Multilevel Interconnect Model Evaluator reads the characterized geometric parameters and generates maximum-, nominal-, and minimum-case parameterized interconnect SPICE subcircuits for each technology to model global and critical VLSI interconnect networks, such as clock trees, power distribution, control/data buses, and word/bit lines. In this way, new interconnect options can be evaluated using rigorous SPICE simulations.