On the use of model checking for the verification of a dynamic signature monitoring approach

Consequences of transient faults represent a significant problem for today's electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is mandatory. It is well known that traditional techniques that validate system's reliability do not cover the whole spectrum of fault scenarios, because fault models are linked to target architectures. Therefore, validating the completeness of robust fault tolerance techniques is a major issue when assessing reliability improvements these techniques can produce. In this paper, we propose an original approach to evaluate the system reliability with respect to Single Event Upset (SEU) errors. It is based on model-checking principles. In addition, a signature analysis technique is evaluated. This technique was previously validated using a simulation-based fault injection approach. Simulation results showed that no error escapes detection. However, simulation based fault injection cannot guarantee that all fault consequences have been investigated. This limitation motivates us to explore a formal verification approach that targets a complete validation. Model checking has a fundamental advantage over classic fault-injection techniques: it can cover all possible SEU fault scenarios from a predefined class. Results reported in this paper demonstrate the efficiency of this validation approach over usual simulation-based techniques.

[1]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[2]  Raoul Velazco,et al.  Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits , 1994 .

[3]  Suku Nair,et al.  Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection , 1999, IEEE Trans. Parallel Distributed Syst..

[4]  Michael Nicolaidis,et al.  Embedded robustness IPs for transient-error-free ICs , 2002, IEEE Design & Test of Computers.

[5]  Jonathan K. Millen,et al.  Verifying Security , 1981, CSUR.

[6]  Pedro J. Gil,et al.  Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System , 1999, EDCC.

[7]  Shin Nakajima,et al.  The SPIN Model Checker : Primer and Reference Manual , 2004 .

[8]  Massimo Violante,et al.  Soft-error detection using control flow assertions , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  Philippe Schnoebelen,et al.  Systems and Software Verification, Model-Checking Techniques and Tools , 2001 .

[10]  Edward J. McCluskey,et al.  Error detection by duplicated instructions in super-scalar processors , 2002, IEEE Trans. Reliab..

[11]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[12]  Y. Savaria,et al.  Software detection mechanisms providing full coverage against single bit-flip faults , 2004, IEEE Transactions on Nuclear Science.

[13]  Prithviraj Banerjee,et al.  Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions , 1992, ICPP.

[14]  Massimo Violante,et al.  New techniques for accelerating fault injection in VHDL descriptions , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[15]  Raoul Velazco,et al.  Injecting bit flip faults by means of a purely software approach: a case studied , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[16]  Edward J. McCluskey,et al.  Control-flow checking by software signatures , 2002, IEEE Trans. Reliab..

[17]  E. Normand Single-event effects in avionics , 1996 .

[18]  Nur A. Touba,et al.  Logic synthesis of multilevel circuits with concurrent error detection , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  S. Rezgui,et al.  Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection , 2000 .

[20]  Yvon Savaria,et al.  Performance evaluation and failure rate prediction for the soft implemented error detection technique , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[21]  Carl E. Landwehr,et al.  Formal Models for Computer Security , 1981, CSUR.

[22]  Stephen S. Yau,et al.  An Approach to Concurrent Control Flow Checking , 1980, IEEE Transactions on Software Engineering.

[23]  R. Velazco,et al.  Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors , 2000 .