The design of the VLSI image-generator ZaP

The authors present the design of 'zoom and pan' (ZaP), a complex 160K-transistor delay-insensitive VLSI circuit. ZaP generates images from structured geometric data with a performance of a million boxes per second. A VLSI program is derived from a formal specification of ZaP though stepwise refinement and decomposition. The subsequent silicon compilation is described briefly. It is concluded that ZaP demonstrates that the design of 'systems on silicon' can be seen as a VLSI-programming activity, to be carried out by system designers.<<ETX>>

[1]  C.H. van Berkel,et al.  Compilations of communicating processes into delay-insensitive circuits , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[2]  M. Rem,et al.  VLSI programming and silicon compilation-a novel approach from Philips research , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[3]  M. Rem,et al.  VLSI programming , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.