Reducing the number of transistors in digital circuits using gate-level evolutionary design

This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In addition to standard gates, we utilize unconventional gates (such as the NAND/NOR gate and NOR/NAND gate) that consist of a few transistors but exhibit non-trivial 3-input logic functions. Novel implementations of adders and majority circuits evolved using these gates contain fewer transistors than the smallest existing implementations of these circuits. Moreover, it was shown that the use of these gates significantly improves the success rate of the search process.

[1]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[2]  Donald E. Knuth,et al.  The art of computer programming: sorting and searching (volume 3) , 1973 .

[3]  Takafumi Aoki,et al.  Evolutionary Synthesis of Arithmetic Circuit Structures , 2003, Artificial Intelligence Review.

[4]  Vu Duong,et al.  Evolution of analog circuits on field programmable transistor arrays , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[5]  John F. Wakerly,et al.  Digital design - principles and practices , 1990, Prentice Hall Series in computer engineering.

[6]  John R. Koza,et al.  Routine human-competitive machine intelligence by means of genetic programming , 2004, SPIE Optics + Photonics.

[7]  Adrian Thompson,et al.  Silicon evolution , 1996 .

[8]  Peter J. Bentley,et al.  Evolving Hardware , 2006, Handbook of Nature-Inspired and Innovative Computing.

[9]  Ricardo Salem Zebulum,et al.  Evolutionary Electronics , 2001 .

[10]  Tatsuo Higuchi,et al.  Graph-based evolutionary design of arithmetic circuits , 2002, IEEE Trans. Evol. Comput..

[11]  Rajiv Gupta,et al.  Low-Power Logic Styles : CMOS vs CPL , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[12]  Julian Francis Miller,et al.  Redundancy and computational efficiency in Cartesian genetic programming , 2006, IEEE Transactions on Evolutionary Computation.

[13]  John R. Koza,et al.  Genetic Programming III: Darwinian Invention & Problem Solving , 1999 .

[14]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[15]  Jörg Langeheine,et al.  Intrinsic Hardware Evolution on the Transistor Level , 2005 .

[16]  Julian Francis Miller,et al.  Scalability problems of digital circuit evolution evolvability and efficient designs , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[17]  Donald E. Knuth,et al.  The art of computer programming, volume 3: (2nd ed.) sorting and searching , 1998 .

[18]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[19]  John R. Koza,et al.  Genetic Programming IV: Routine Human-Competitive Machine Intelligence , 2003 .

[20]  Esther Rodríguez-Villegas,et al.  Practical low-cost CPL implementations threshold logic functions , 2001, GLSVLSI '01.

[21]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[22]  Licheng Jiao,et al.  Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm , 2006, Genetic Programming and Evolvable Machines.

[23]  John R. Koza Genetic Programming III - Darwinian Invention and Problem Solving , 1999, Evolutionary Computation.

[24]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[25]  Kuo-Hsing Cheng,et al.  High efficient 3-input XOR for low-voltage low-power high-speed applications , 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).