A new CMOS charge pump for low-voltage (1V) high-speed PLL applications

This paper proposes a new charge pump structure for phase locked loop (PLL) applications. The circuit is optimized to minimize the amount of glitches in the output current. It is designed in a standard CMOS 0.18/spl mu/m technology, and it operates from a 1V power supply. The output voltage has a relatively wide range, from 100mV up to 900mV, and does not exhibit any spurious jump phenomenon. Simulation results in HSPICE show the capability of high-frequency operation (500MHz), with very low-power consumption (60/spl mu/W).

[1]  Chih-Ming Hung,et al.  A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop , 2002, IEEE J. Solid State Circuits.

[2]  E.J. Hernandez,et al.  Positive feedback CMOS charge-pump circuits for PLL applications , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

[3]  Woo-Young Choi,et al.  A novel charge pump PLL with reduced jitter characteristics , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[4]  R.C. Chang,et al.  A new low-voltage charge pump circuit for PLL , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[5]  J. Bock,et al.  45 GHz highly integrated phase-locked loop frequency synthesizer in SiGe bipolar technology , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[6]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[7]  Mourad N. El-Gamal,et al.  A Sub-1-V 4-GHz CMOS VCO and a 12.5-GHz oscillator for low-voltage and high-frequency applications , 2001 .

[8]  Robert Weigel,et al.  Design of a novel low-power 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800 , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[9]  Behzad Razavi,et al.  A 6 GHz 60 mW BiCMOS phase-locked loop with 2 V supply , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[10]  Guido Torelli,et al.  A sigma-delta based PLL for non-sinusoidal waveforms , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.