Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

This paper proposes a novel voltage scaling low-power design methodology for large system-on-chip (SoC) designs. It scales the supply voltage to a SoC based on operating conditions and bit error rate in a system. It allows occasional timing errors in the circuit and relies on a forward error correction that already exists in the system to correct the errors. As a result, the proposed technique imposes no hardware overhead yet yields significant power savings. More importantly, it does not require any circuit modification based on place and route, thus it is easy to implement and has no impact for time to market. The new technique was implemented in a complex telecom SoC design, and silicon measurements show power savings up to 50% for free.

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