The Nanoscale Silicon Accumulation-Mode MOSFET—A Comprehensive Numerical Study

Recently, we proposed and experimentally demonstrated a very simply structured unipolar accumulation-type field- effect transistor (FET) using silicon nanowires (NWs). In this paper, we present an extensive numerical study of this accumulation metal-oxide-semiconductor FET (AMOSFET). This single-doping-type ohmically contacted structure relies on having a nanoscale dimension normal to the gate, thereby forcing the current path through an accumulated (ON-state) or depleted (OFF-state) region. It also relies on having contact-barrier and doping-dependent minimum source and drain lengths as well as minimum gate lengths to insure unipolar transistor action. The comprehensive report presented extends our previous examination of the device's operation by using extensive numerical simulations to offer a greater understanding of the origins of transistor operation. We explore a wide range of structural and material parameters to study their effects on the linear, saturation, and OFF-state currents. We also delve deeper into the uniquely weak dependence on gate capacitance. This paper establishes that this extremely simple accumulation-mode transistor structure offers its best performance for the more highly doped thinnest devices, giving, for example, for a 1017-cm-3 (doping) and 20-nm device a leakage current of ~40-17 A/mum, a subthreshold swing of 65 mV/dec, and an on-off ratio approximately 1010. This paper also shows that such results should be attainable for AMOSFETs fabricated using NWs and nanoribbons, as well as nanoscale thin-film materials.

[1]  S. Fonash,et al.  Self-assembling silicon nanowires for device applications using the nanochannel-guided "grow-in-place" approach. , 2008, ACS nano.

[2]  J. Fischer,et al.  Synthesis and postgrowth doping of silicon nanowires , 2005 .

[3]  G. Masetti,et al.  Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon , 1983, IEEE Transactions on Electron Devices.

[4]  S. Fonash,et al.  High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs , 2005, IEEE Electron Device Letters.

[5]  T. Sugii,et al.  MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[6]  Xiangfeng Duan,et al.  High-performance thin-film transistors using semiconductor nanowires and nanoribbons , 2003, Nature.

[7]  K. Ng,et al.  The Physics of Semiconductor Devices , 2019, Springer Proceedings in Physics.

[8]  J. Kavalieros,et al.  High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.

[9]  S.C. Rustagi,et al.  High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices , 2006, IEEE Electron Device Letters.

[10]  Charles M. Lieber,et al.  Nonvolatile Memory and Programmable Logic from Molecule-Gated Nanowires , 2002 .

[11]  S. Wagner,et al.  Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250/spl deg/C to 280/spl deg/ C , 2006, IEEE Electron Device Letters.

[12]  Wu Wang,et al.  High-Performance Nanowire Electronics and Photonics on Glass and Plastic Substrates , 2003 .

[13]  Massimo Vanzi,et al.  A physically based mobility model for numerical simulation of nonplanar devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Unipolar accumulation-type transistor configuration implemented using Si nanowires , 2007 .

[15]  Charles M. Lieber,et al.  Ge/Si nanowire heterostructures as high-performance field-effect transistors , 2006, Nature.

[16]  Chenming Hu,et al.  5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[17]  Suman Datta,et al.  High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .

[18]  A. Nathan,et al.  Amorphous silicon display backplanes on plastic substrates , 2005 .

[19]  Gerhard Klimeck,et al.  Performance analysis of a Ge/Si core/shell nanowire field-effect transistor. , 2006, Nano letters.

[20]  C. Lieber,et al.  Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species , 2001, Science.

[21]  Xuema Li,et al.  Sequence-Specific Label-Free DNA Sensors Based on Silicon Nanowires , 2004 .

[22]  C. Canali,et al.  Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature , 1975, IEEE Transactions on Electron Devices.

[23]  Numerical modeling study of the unipolar accumulation transistor , 2007 .