AHigh-Speed, Low-Complexity Radix-24FFT Processor forMB-OFDM UWB Systems

Thispaperpresents thearchitecture design ofa 7 4 A s ~~~~~~JIb7IIc R emove o nts emapiong eoe high-speed, low-complexity 128-point radix-24 FFT processor Re_moIe tFEQ Pots Deterleaver rambler forultra-wideband (UJWB) systems. Theproposed high-speed, low-complexity FFT architecture can providea higher =4 Meanstwodatapath CarrerPhase throughput rateandlowhardwarecomplexity byusing2- - Meansonedatapath TimeTracking parallel data-path schemeandsingle-path delay-feedback (SDF)structure. Thispaperpresents thekeyideas applied to Figure 1. Block diagram oftheMB-OFDMUWBreceiver system thedesign ofhigh-speed, low-complexity FFT processor, especially thatforachieving highthroughput rateand Thispaperisorganized asfollows. Section IIdescribes reducing hardware complexity. Theproposed FFTprocessorthedesign issues ofMB-OFDM UWB communication hasbeendesigned andimplemented withthe0.18-gm CMOS systems. Section IIIdescribes the128-point radix-24 FFT technology inasupply voltage of1.8V.Thethroughput rate of algorithm. Section IVfocuses ondescribing theproposed proposed FFTprocessor isupto1Gsample/s while itrequiresFFT architecture. In Section V, theproposed FFT muchsmaller hardware complexity. architecture compares its hardware costandthroughput rate withsomeexisting FFTarchitectures in128-point FFT.Then, I. INTRODUCTION conclusions aredrawninSection VI.