Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs
暂无分享,去创建一个
[1] Wolfgang Hohl,et al. Multiprocessor Checking Using Watchdog Processors , 1996 .
[2] Rob A. Rutenbar,et al. (When) will FPGAs kill ASICs? (panel session) , 2001, DAC '01.
[3] Gang Qu,et al. Publicly detectable watermarking for intellectual property authentication in VLSI design , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Crispin Cowan,et al. FormatGuard: Automatic Protection From printf Format String Vulnerabilities , 2001, USENIX Security Symposium.
[5] A. One,et al. Smashing The Stack For Fun And Profit , 1996 .
[6] Christopher Krügel,et al. Run-time Detection of Heap-based Overflows , 2003, LISA.
[7] M. Rimen,et al. Implicit signature checking , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[8] Amr T. Abdel-Hamid,et al. A Survey on IP Watermarking Techniques , 2004, Des. Autom. Embed. Syst..
[9] Marc Tremblay,et al. High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback , 1990, IEEE Trans. Computers.
[10] A. Johnston. Scaling and Technology Issues for Soft Error Rates , 2000 .
[11] D.R. Kaeli,et al. Branch history table prediction of moving target branches due to subroutine returns , 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.
[12] Daniel P. Siewiorek,et al. Reliable computer systems (2nd ed.): design and evaluation , 1992 .
[13] G. Edward Suh,et al. Extracting secret keys from integrated circuits , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] Husrev T. Sencar,et al. Security issues in watermarking applications - a deeper look , 2006, MCPS '06.
[15] Ramesh Karri,et al. Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[17] Stephanie Forrest,et al. Intrusion Detection Using Sequences of System Calls , 1998, J. Comput. Secur..
[18] J.E. Mazo,et al. Digital communications , 1985, Proceedings of the IEEE.
[19] Olatunji Ruwase,et al. A Practical Dynamic Buffer Overflow Detector , 2004, NDSS.
[20] Miodrag Potkonjak,et al. Robust IP watermarking methodologies for physical design , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[21] Trevor Mudge,et al. MiBench: A free, commercially representative embedded benchmark suite , 2001 .
[22] Philip R. Zimmermann,et al. The official PGP user's guide , 1996 .
[23] E. Castillo,et al. Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection , 2008, 2008 4th Southern Conference on Programmable Logic.
[24] Marten van Dijk,et al. A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[25] A. Singh,et al. Fault-tolerant systems , 1990, Computer.
[26] Shambhu J. Upadhyaya,et al. Concurrent Process Monitoring with No Reference Signatures , 1994, IEEE Trans. Computers.
[27] Miodrag Potkonjak,et al. Behavioral synthesis techniques for intellectual property protection , 2005, TODE.
[28] Carl E. Landwehr,et al. Basic concepts and taxonomy of dependable and secure computing , 2004, IEEE Transactions on Dependable and Secure Computing.
[29] Ravishankar K. Iyer,et al. An architectural framework for providing reliability and security support , 2004, International Conference on Dependable Systems and Networks, 2004.
[30] James Cheney,et al. Cyclone: A Safe Dialect of C , 2002, USENIX Annual Technical Conference, General Track.
[31] Matt Bishop,et al. Testing C Programs for Buffer Overflow Vulnerabilities , 2003, NDSS.
[32] R.D. Schrimpf,et al. Single event transient pulse widths in digital microcircuits , 2004, IEEE Transactions on Nuclear Science.
[33] Zeljko Zilic,et al. Using BDDs to Design ULMs for FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[34] Jawad A. Salehi,et al. Code division multiple-access techniques in optical fiber networks. II. Systems performance analysis , 1989, IEEE Trans. Commun..
[35] Miodrag Potkonjak,et al. Fingerprinting techniques for field-programmable gate arrayintellectual property protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[36] David A. Wagner,et al. Intrusion detection via static analysis , 2001, Proceedings 2001 IEEE Symposium on Security and Privacy. S&P 2001.
[37] Babak Falsafi,et al. Dual use of superscalar datapath for transient-fault detection and recovery , 2001, MICRO.
[38] A. K. Ray,et al. Electromigration―a tutorial introduction , 1990 .
[39] Michael B. Gordy. GA.M: A Matlab routine for function maximization using a Genetic Algorithm , 1996 .
[40] Ming Zhang,et al. Soft Error Resilient System Design through Error Correction , 2006, 2006 IFIP International Conference on Very Large Scale Integration.
[41] Kenneth B. Kent,et al. Periodic licensing of FPGA based intellectual property , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[42] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[43] James P Anderson,et al. Computer Security Technology Planning Study , 1972 .
[44] Yiorgos Makris,et al. Concurrent error detection for combinational and sequential logic via output compaction , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[45] Algirdas Avizienis,et al. The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design , 1971, IEEE Transactions on Computers.
[46] Saar Drimer,et al. Security for volatile FPGAs , 2009 .
[47] Daniel C. DuVarney,et al. Address Obfuscation: An Efficient Approach to Combat a Broad Range of Memory Error Exploits , 2003, USENIX Security Symposium.
[48] Ralf Seepold. Special session—virtual socket interface alliance , 1999, DATE '99.
[49] Michael Mueller,et al. RAS strategy for IBM S/390 G5 and G6 , 1999, IBM J. Res. Dev..
[50] David L. Weaver,et al. The SPARC Architecture Manual , 2003 .
[51] M. Nicolaidis,et al. Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD 2003.
[52] Spyros Tragoudas,et al. Rewiring for watermarking digital circuit netlists , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[53] G. Morrisett,et al. Cyclone : A Type-Safe Dialect of C ∗ , 2004 .
[54] Ronald L. Rivest,et al. The MD5 Message-Digest Algorithm , 1992, RFC.
[55] Norbert Wehn,et al. Concepts for Autonomic Integrated Systems , 2007 .
[56] Wolfgang Rosenstiel,et al. Organic Computing at the System on Chip Level , 2006, 2006 IFIP International Conference on Very Large Scale Integration.
[57] Cheng Wang,et al. Software-based transparent and comprehensive control-flow error detection , 2006, International Symposium on Code Generation and Optimization (CGO'06).
[58] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[59] Tariq S. Durrani,et al. IP protection of DSP algorithms for system on chip implementation , 2000, IEEE Trans. Signal Process..
[60] Jiri Gaisler. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture , 2002, Proceedings International Conference on Dependable Systems and Networks.
[61] Robert O. Hastings,et al. Fast detection of memory leaks and access errors , 1991 .
[62] Cristina Cifuentes,et al. Recovery of jump table case statements from binary code , 1999, Proceedings Seventh International Workshop on Program Comprehension.
[63] Gang Qu,et al. Zero overhead watermarking technique for FPGA designs , 2003, GLSVLSI '03.
[64] Edward J. McCluskey,et al. ED4I: Error Detection by Diverse Data and Duplicated Instructions , 2002, IEEE Trans. Computers.
[65] K. Sundaramoorthy,et al. Slipstream processors: improving both performance and fault tolerance , 2000, SIGP.
[66] Edward J. McCluskey,et al. Control-flow checking using watchdog assists and extended-precision checksums , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[67] John F. Meyer,et al. Fault Tolerant Sequential Machines , 1971, IEEE Transactions on Computers.
[68] Massimo Violante,et al. Soft-error detection using control flow assertions , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.
[69] Régis Leveugle,et al. A new approach to control flow checking without program modification , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.
[70] Jacob A. Abraham,et al. Evaluation of integrated system-level checks for on-line error detection , 1996, Proceedings of IEEE International Computer Performance and Dependability Symposium.
[71] Stephanie Forrest,et al. A sense of self for Unix processes , 1996, Proceedings 1996 IEEE Symposium on Security and Privacy.
[72] Fan Chung Graham,et al. Optical orthogonal codes: Design, analysis, and applications , 1989, IEEE Trans. Inf. Theory.
[73] I. Torunoglu,et al. Watermarking-based copyright protection of sequential functions , 2000, IEEE Journal of Solid-State Circuits.
[74] Edward J. McCluskey,et al. Control-flow checking by software signatures , 2002, IEEE Trans. Reliab..
[75] William R. Bush,et al. A static analyzer for finding dynamic programming errors , 2000, Softw. Pract. Exp..
[76] Rolf Ernst,et al. Reliability Analysis of Single Bus Communication with Real-Time Requirements , 2009, 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing.
[77] Todd M. Austin,et al. Fault-based attack of RSA authentication , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[78] Edward J. McCluskey,et al. Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[79] David J. Lu. Watchdog Processors and Structural Integrity Checking , 1982, IEEE Transactions on Computers.
[80] P. D. Prewett. FOCUSED ION BEAMS IN MICROFABRICATION , 1989 .
[81] Kewal K. Saluja,et al. Fault tolerance through re-execution in multiscalar architecture , 2000, Proceeding International Conference on Dependable Systems and Networks. DSN 2000.
[82] Ruby B. Lee,et al. Enlisting Hardware Architecture to Thwart Malicious Code Injection , 2004, SPC.
[83] John Johansen,et al. PointGuard™: Protecting Pointers from Buffer Overflow Vulnerabilities , 2003, USENIX Security Symposium.
[84] Jürgen Teich,et al. Netlist-level IP protection by watermarking for LUT-based FPGAs , 2008, 2008 International Conference on Field-Programmable Technology.
[85] Steve J. Chapin,et al. Type-Assisted Dynamic Buffer Overflow Detection , 2002, USENIX Security Symposium.
[86] Miodrag Potkonjak,et al. Techniques for Design and Implementation of Secure Reconfigurable PUFs , 2009, TRETS.
[87] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.
[88] A. Viterbi. CDMA: Principles of Spread Spectrum Communication , 1995 .
[89] Paul H. J. Kelly,et al. Backwards-Compatible Bounds Checking for Arrays and Pointers in C Programs , 1997, AADEBUG.
[90] Andrew J. Viterbi,et al. Very Low Rate Convolutional Codes for Maximum Theoretical Performance of Spread-Spectrum Multiple-Access Channels , 1990, IEEE J. Sel. Areas Commun..
[91] N. Seifert,et al. Robust system design with built-in soft-error resilience , 2005, Computer.
[92] Norbert Wehn,et al. Autonomic MPSoCs for Reliable Systems , 2007 .
[93] John Paul Shen,et al. Continuous signature monitoring: low-cost concurrent detection of processor control errors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[94] Irith Pomeranz,et al. Transient-fault recovery using simultaneous multithreading , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[95] Ahmed H. Tewfik,et al. Digital watermarks for audio signals , 1996, 1996 8th European Signal Processing Conference (EUSIPCO 1996).
[96] Patrick Schaumont,et al. Offline Hardware/Software Authentication for Reconfigurable Platforms , 2006, CHES.
[97] Shekhar Y. Borkar,et al. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.
[98] Giovanni De Micheli. Designing Robust Systems with Uncertain Information , 2003 .
[99] Irith Pomeranz,et al. Transient-fault recovery for chip multiprocessors , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..
[100] Heinrich Theodor Vierhaus,et al. Online Check and Recovery Techniques for Dependable Embedded Processors , 2001, IEEE Micro.
[101] Navjot Singh,et al. Transparent Run-Time Defense Against Stack-Smashing Attacks , 2000, USENIX Annual Technical Conference, General Track.
[102] Miodrag Potkonjak,et al. Watermarking techniques for intellectual property protection , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[103] Zhiqiang Gao,et al. A Watermarking Technique for Hard IP Protection in Full-custom IC Design , 2007, 2007 International Conference on Communications, Circuits and Systems.
[104] Michael Nicolaidis,et al. Efficient implementations of self-checking adders and ALUs , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[105] Alan O. Freier,et al. The SSL Protocol Version 3.0 , 1996 .
[106] Wolfgang Hohl,et al. Concurrent Error Detection Using Watchdog Processors in the Multiprocessor System MEMSY , 1991 .
[107] K. Soumyanath,et al. Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[108] J. Goldberg,et al. SIFT: Design and analysis of a fault-tolerant computer for aircraft control , 1978, Proceedings of the IEEE.
[109] Mona Attariyan,et al. Low-Cost Protection for SER Upsets and Silicon Defects , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[110] Bruce Schneier,et al. Practical cryptography , 2003 .
[111] Jeffrey M. Nick,et al. S/390 Cluster Technology: Parallel Sysplex , 1997, IBM Syst. J..
[112] Michael Shuey,et al. StackGhost: Hardware Facilitated Stack Protection , 2001, USENIX Security Symposium.
[113] David Blaauw,et al. Making typical silicon matter with Razor , 2004, Computer.
[114] Dakshi Agrawal,et al. The EM Side-Channel(s) , 2002, CHES.
[115] Ee-Chien Chang,et al. Zero-knowledge watermark detection resistant to ambiguity attacks , 2006, MM&Sec '06.
[116] Masood Namjoo,et al. Techniques for Concurrent Testing of VLSI Processor Operation , 1982, ITC.
[117] Manoj Franklin. A study of time redundant fault tolerance techniques for superscalar processors , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.
[118] Daniel E. Holcomb,et al. Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags , 2007 .
[119] Norbert Wehn,et al. A rapid prototyping system for error-resilient multi-processor systems-on-chip , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[120] Albert Meixner,et al. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[121] Jürgen Teich,et al. Power Signature Watermarking of IP Cores for FPGAs , 2008, J. Signal Process. Syst..
[122] N. R. Alamelu,et al. SELF CHECKING AND FAULT TOLERANT DIGITAL DESIGN , 2009 .
[123] Jürgen Teich. Digitale Hardware/Software-Systeme - Synthese und Optimierung , 1997 .
[124] Jürgen Teich,et al. Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs , 2009, Int. J. Auton. Adapt. Commun. Syst..
[125] Ronald L. Rivest,et al. The RC4 encryption algorithm , 1992 .
[126] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[127] Joel F. Bartlett,et al. A NonStop kernel , 1981, SOSP.
[128] M. Baze,et al. Comparison of error rates in combinational and sequential logic , 1997 .
[129] Jürgen Teich,et al. Multiplexing methods for power watermarking , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).
[130] J.D. Carothers,et al. IP protection for VLSI designs via watermarking of routes , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[131] Andreas Krennmair. ContraPolice: a libc Extension for Protecting Applications from Heap-Smashing Attacks , 2003 .
[132] R.C. Baumann,et al. Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.
[133] Michael Rodeh,et al. CSSV: towards a realistic tool for statically detecting all buffer overflows in C , 2003, PLDI '03.
[134] Tsutomu Sasao,et al. Fast Boolean matching under permutation using representative , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).
[135] Shubhendu S. Mukherjee,et al. Transient fault detection via simultaneous multithreading , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[136] Jürgen Teich,et al. ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[137] Jürgen Teich,et al. Using the Power Side Channel of FPGAs for Communication , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.
[138] Martín Abadi,et al. Architectural support for software-based protection , 2006, ASID '06.
[139] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[140] Miodrag Potkonjak,et al. Robust FPGA intellectual property protection through multiple small watermarks , 1999, DAC '99.
[141] Suchai Thanawastien,et al. An SFS Berger check prediction ALU and its application to self-checking processor designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[142] M. Kuhn,et al. The Advanced Computing Systems Association Design Principles for Tamper-resistant Smartcard Processors Design Principles for Tamper-resistant Smartcard Processors , 2022 .
[143] Paul C. Kocher,et al. Differential Power Analysis , 1999, CRYPTO.
[144] Úlfar Erlingsson,et al. Low-Level Software Security: Attacks and Defenses , 2007, FOSAD.
[145] Sule Ozev,et al. Online diagnosis of hard faults in microprocessors , 2007, TACO.
[146] E. A. Wolicki,et al. Single Event Upset of Dynamic Rams by Neutrons and Protons , 1979, IEEE Transactions on Nuclear Science.
[147] Stephen S. Yau,et al. An Approach to Concurrent Control Flow Checking , 1980, IEEE Transactions on Software Engineering.
[148] David Evans,et al. Improving Security Using Extensible Lightweight Static Analysis , 2002, IEEE Softw..
[149] Jorge Guajardo,et al. FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.
[150] Sanjay J. Patel,et al. ReStore: symptom based soft error detection in microprocessors , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).
[151] Srivaths Ravi,et al. Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[152] Ravishankar K. Iyer,et al. A framework for database audit and control flow checking for a wireless telephone network controller , 2001, 2001 International Conference on Dependable Systems and Networks.
[153] Edoardo Charbon. Hierarchical watermarking in IC design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
[154] Todd C. Miller,et al. strlcpy and strlcat - Consistent, Safe, String Copy and Concatenation , 1999, USENIX Annual Technical Conference, FREENIX Track.
[155] Ravishankar K. Iyer,et al. Transparent runtime randomization for security , 2003, 22nd International Symposium on Reliable Distributed Systems, 2003. Proceedings..
[156] Yi He,et al. Defending embedded systems against buffer overflow via hardware/software , 2003, 19th Annual Computer Security Applications Conference, 2003. Proceedings..
[157] Hen-Wai Tsao,et al. Watermarking for intellectual property protection , 2003 .
[158] Martín Abadi,et al. XFI: software guards for system address spaces , 2006, OSDI '06.
[159] Michael Nicolaidis. Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[160] A. Bravaix,et al. The Energy-Driven Hot-Carrier Degradation Modes of nMOSFETs , 2007, IEEE Transactions on Device and Materials Reliability.
[161] Yvo Desmedt,et al. Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection , 2002, Information Hiding.
[162] David H. Ackley,et al. Randomized instruction set emulation , 2005, TSEC.
[163] Markus G. Kuhn,et al. Tamper resistance: a cautionary note , 1996 .
[164] Jawad A. Salehi,et al. Code division multiple-access techniques in optical fiber networks. I. Fundamental principles , 1989, IEEE Trans. Commun..
[165] Edward J. McCluskey,et al. Concurrent Error Detection Using Watchdog Processors - A Survey , 1988, IEEE Trans. Computers.
[166] Christian Haubelt,et al. Efficient Reconfigurable On-Chip Buses for FPGAs , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.
[167] Nur A. Touba,et al. Logic synthesis of multilevel circuits with concurrent error detection , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[168] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[169] Hermann Kopetz,et al. Real-time systems , 2018, CSC '73.
[170] Jonathan Grudin,et al. Design and evaluation , 1995 .
[171] Paul C. Kocher,et al. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.
[172] Gary McGraw,et al. ITS4: a static vulnerability scanner for C and C++ code , 2000, Proceedings 16th Annual Computer Security Applications Conference (ACSAC'00).
[173] Carla E. Brodley,et al. SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address , 2006, IEEE Transactions on Computers.
[174] K. Mani Chandy,et al. A Survey of Analytic Models of Rollback and Recovery Stratergies , 1975, Computer.
[175] Narayanan Vijaykrishnan,et al. Reliability concerns in embedded system designs , 2006, Computer.
[176] Arlindo L. Oliveira. Techniques for the creation of digital watermarks in sequentialcircuit designs , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[177] Whitfield Diffie,et al. New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.
[178] Yale N. Patt,et al. Target prediction for indirect jumps , 1997, ISCA '97.
[179] Tzi-cker Chiueh,et al. RAD: a compile-time solution to buffer overflow attacks , 2001, Proceedings 21st International Conference on Distributed Computing Systems.
[180] Hovav Shacham,et al. When good instructions go bad: generalizing return-oriented programming to RISC , 2008, CCS.
[181] Henrique Madeira,et al. On-line signature learning and checking: experimental evaluation , 1991, [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications.
[182] Brian Randell,et al. Fundamental Concepts of Dependability , 2000 .
[183] Angelos D. Keromytis,et al. Countering code-injection attacks with instruction-set randomization , 2003, CCS '03.
[184] Miodrag Potkonjak,et al. Fingerprinting intellectual property using constraint-addition , 2000, DAC.
[185] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[186] Jürgen Teich,et al. Identifying FPGA IP-Cores Based on Lookup Table Content Analysis , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[187] John Paul Shen,et al. Processor Monitoring Using Asynchronous Signatured Instruction Streams , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..
[188] Miodrag Potkonjak,et al. Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[189] John G. Proakis,et al. Digital Communications , 1983 .
[190] Jiri Gaisler. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.
[191] Tom Kean. Secure Configuration of a Field Programmable Gate Array , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).
[192] Li Shang,et al. Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.
[193] William R. Crowther,et al. Pluribus: a reliable multiprocessor , 1975, AFIPS '75.
[194] John Paul Shen,et al. Processor Control Flow Monitoring Using Signatured Instruction Streams , 1987, IEEE Transactions on Computers.
[195] Gerardo Richarte. Four dierent tricks to bypass StackShield and StackGuard protection , 2002, WWW 2002.
[196] M. Violante,et al. Improved software-based processor control-flow errors detection technique , 2005, Annual Reliability and Maintainability Symposium, 2005. Proceedings..
[197] John Paul Shen. A roving monitoring processor for detection of control flow errors in multiple processor systems , 1987 .
[198] A. Glavieux,et al. Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.
[199] Lilian Bossuet,et al. Dynamically configurable security for SRAM FPGA bitstreams , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..
[200] Todd M. Austin,et al. DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.
[201] Tom Kean,et al. Verifying the authenticity of chip designs with the DesignTag system , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.
[202] Calton Pu,et al. Protecting Systems from Stack Smashing Attacks with StackGuard , 1999 .
[203] Onur Mutlu,et al. Dynamic Predication of Indirect Jumps , 2007, IEEE Computer Architecture Letters.
[204] T. N. Vijaykumar,et al. Opportunistic Transient-Fault Detection , 2005, ISCA 2005.
[205] Robert H. Deng,et al. Breaking Public Key Cryptosystems on Tamper Resistant Devices in the Presence of Transient Faults , 1997, Security Protocols Workshop.
[206] Gabriele Saucier,et al. Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors , 1991, 1991, Proceedings. International Test Conference.
[207] Sri Parameswaran,et al. Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[208] Jason Cong,et al. Intellectual property protection by watermarking combinational logic synthesis solutions , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[209] Weibo Gong,et al. Anomaly detection using call stack information , 2003, 2003 Symposium on Security and Privacy, 2003..
[210] Michael Nicolaidis,et al. Fault-Secure Parity Prediction Arithmetic Operators , 1997, IEEE Des. Test Comput..
[212] James R. Larus,et al. Righting software , 2004, IEEE Software.
[213] Frederick F. Sellers,et al. Error detecting logic for digital computers , 1968 .
[214] M. Potkonjak,et al. Hierarchical watermarking for protection of DSP filter cores , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
[215] Eli Biham,et al. Differential Fault Analysis of Secret Key Cryptosystems , 1997, CRYPTO.
[216] Tao Zhang,et al. Anomalous path detection with hardware support , 2005, CASES '05.
[217] Johan Karlsson,et al. Two software techniques for on-line error detection , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.
[218] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[219] G. Edward Suh,et al. Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[220] Jürgen Teich,et al. FPGA core watermarking based on power signature analysis , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[221] Srivaths Ravi,et al. Security as a new dimension in embedded system design , 2004, Proceedings. 41st Design Automation Conference, 2004..
[222] B. Narasimham,et al. Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.
[223] Gabriele Saucier,et al. Control flow checking in pipelined RISC microprocessors: the Motorola MC88100 case study , 1990, Proceedings. EUROMICRO '90 Workshop on Real Time.
[224] Tao Zhang,et al. Hardware Supported Anomaly Detection: down to the Control Flow Level , 2004 .
[225] David A. Wagner,et al. A First Step Towards Automated Detection of Buffer Overrun Vulnerabilities , 2000, NDSS.
[226] Wolfgang Hohl,et al. Watchdog processors in parallel systems , 1993, Microprocess. Microprogramming.
[227] Oliver Bringmann,et al. ESL power analysis of embedded processors for temperature and reliability estimations , 2009, CODES+ISSS '09.
[228] Suku Nair,et al. Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection , 1999, IEEE Trans. Parallel Distributed Syst..
[229] Edwin Hsing-Mean Sha,et al. Security protection and checking in embedded system integration against buffer overflow attacks , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..
[230] Susmita Sur-Kolay,et al. Fast Robust Intellectual Property Protection for VLSI Physical Design , 2007, 10th International Conference on Information Technology (ICIT 2007).
[231] Jun Xu,et al. Architecture Support for Defending Against Buffer Overflow Attacks , 2002 .
[232] FPGA Design Security Solution Using MAX II Devices , 2004 .
[233] Jan A. Bergstra,et al. Instruction Sequences with Indirect Jumps , 2007, Sci. Ann. Comput. Sci..
[234] Mateo Valero,et al. A Comprehensive Analysis of Indirect Branch Prediction , 2002, ISHPC.
[235] Jürgen Teich,et al. Concepts for Autonomous Control Flow Checking for Embedded CPUs , 2008, ATC.
[236] Pankaj Jalote,et al. Fault tolerance in distributed systems , 1994 .
[237] Sule Ozev,et al. Tolerating hard faults in microprocessor array structures , 2004, International Conference on Dependable Systems and Networks, 2004.
[238] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[239] Miodrag Potkonjak,et al. Signature hiding techniques for FPGA intellectual property protection , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[240] David I. August,et al. SWIFT: software implemented fault tolerance , 2005, International Symposium on Code Generation and Optimization.
[241] Miodrag Potkonjak,et al. INTELLECTUAL PROPERTY PROTECTION USING WATERMARKING PARTIAL SCAN CHAINS FOR SEQUENTIAL LOGIC TEST GENERATION , 1998, ICCAD 1998.
[242] Srinivas Devadas,et al. Silicon physical random functions , 2002, CCS '02.
[243] Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices , 2004 .
[245] M. Nicolaidis,et al. Evaluation of a soft error tolerance technique based on time and/or space redundancy , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).
[246] Ahmad-Reza Sadeghi,et al. Overcoming the obstacles of zero-knowledge watermark detection , 2004, MM&Sec '04.
[247] Anup Kumar Ghosh,et al. Analyzing Programs for Vulnerability to Buffer Overrun Attacks , 1998 .
[248] Todd M. Austin,et al. A fault tolerant approach to microprocessor design , 2001, 2001 International Conference on Dependable Systems and Networks.
[249] Eric Rotenberg,et al. AR-SMT: a microarchitectural approach to fault tolerance in microprocessors , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[250] George C. Necula,et al. CCured: type-safe retrofitting of legacy software , 2005, TOPL.
[251] Crispan Cowan,et al. StackGuard: Automatic Adaptive Detection and Prevention of Buffer-Overflow Attacks , 1998, USENIX Security Symposium.
[252] Dwight L. Crook,et al. Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown , 1979, 17th International Reliability Physics Symposium.
[253] Lynn Youngs,et al. Mapping and Repairing Embedded-Memory Defects , 1997, IEEE Des. Test Comput..
[254] Joel S. Emer,et al. Techniques to reduce the soft error rate of a high-performance microprocessor , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[255] Michael A. Harrison,et al. Introduction to switching and automata theory , 1965 .
[256] R. Sekar,et al. A fast automaton-based method for detecting anomalous program behaviors , 2001, Proceedings 2001 IEEE Symposium on Security and Privacy. S&P 2001.
[257] Satish M. Thatte,et al. Concurrent Checking of Program Flow in VLSI Processors , 1982, ITC.
[258] Srivaths Ravi,et al. Security in embedded systems: Design challenges , 2004, TECS.
[259] Hovav Shacham,et al. The geometry of innocent flesh on the bone: return-into-libc without function calls (on the x86) , 2007, CCS '07.
[260] Vivek De,et al. Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process , 2004 .
[261] S. Bagchi,et al. Design and Evaluation of Preemptive Control Signature ( PECOS ) Checking , 2003 .
[262] James R. Larus,et al. Rewriting executable files to measure program behavior , 1994, Softw. Pract. Exp..
[263] 곽순섭,et al. Generalized Functions , 2006, Theoretical and Mathematical Physics.
[264] Miodrag Potkonjak,et al. Watermarking while preserving the critical path , 2000, Proceedings 37th Design Automation Conference.
[265] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .
[266] Ruby B. Lee,et al. A processor architecture defense against buffer overflow attacks , 2003, International Conference on Information Technology: Research and Education, 2003. Proceedings. ITRE2003..
[267] Eric Rotenberg,et al. Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance , 2006, ASPLOS XII.
[268] John Lane,et al. IEEE Standard Computer Dictionary: Compilation of IEEE Standard Computer Glossaries , 1991 .
[269] Jonathan D. Pincus,et al. Beyond stack smashing: recent advances in exploiting buffer overruns , 2004, IEEE Security & Privacy Magazine.
[270] Carl E. Landwehr,et al. A taxonomy of computer program security flaws , 1993, CSUR.