Noise in deep submicron digital design

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

[1]  Jacek M. Zurada,et al.  Dynamic noise margins of MOS logic gates , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Norman P. Jouppi.  Derivation of Signal Flow Direction in MOS VLSI , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Robert H. Dennard,et al.  Modeling and characterization of long on-chip interconnections for high-performance microprocessors , 1995, IBM Journal of Research and Development.

[4]  Yuan Taur,et al.  A half-micron CMOS logic generation , 1995, IBM J. Res. Dev..

[5]  Arvind Srinivasan,et al.  Verity - A formal verification program for custom CMOS circuits , 1995, IBM J. Res. Dev..

[6]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[7]  Ronald A. Rohrer,et al.  Sensitivity computation in piecewise approximate circuit simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  G.A. Katopis,et al.  Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[9]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[10]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  R. Rohrer.  The Generalized Adjoint Network and Network Sensitivities , 1969 .

[13]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  Automation of IC layout with analog constraints , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Daniel W. Dobberpuhl,et al.  The design and analysis of VLSI circuits , 1985 .

[16]  T. J. Schmerbeck,et al.  A CMOS-based analog standard cell product family , 1989 .

[17]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[18]  H. H. Chen,et al.  Minimizing chip-level simultaneous switching noise for high-performance microprocessor design , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[19]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..