Simulation of HSTL IO standard based energy efficient Punjabi Unicode reader on FPGA

Punjabi is ranked 1st in languages of Pakistan [5], 11th in Indian languages [6] and 3rd in Indian Subcontinent. In order to write Punjabi: Gurmukhi script is used in India and Shahmukhi in Pakistan. A lot of research is going on in Pakistan and India in the domain of natural language processing but, no research group is working especially for Punjabi to design Unicode reader. The Unicode range of characters for Gurmukhi script is 0x0A01-0x0A75. In this work, we are trying to fill this research gap in Punjabi natural language processing. This paper covers the hardware design and implementation of Punjabi Unicode Reader (PUR) for Gurmukhi scripts on Virtex-6 FPGA. This PUR design was tested with device operating frequency of 25 MHz, 125 MHz, 625 MHz, 1 GHz and 25 GHz. HSTL (High Speed Transceiver Logic) and I/O standard is used to make this design more energy efficient. Using HSTL_I_12, 38-50% I/O power was noticed and while using HSTL_II,the saving increases to 49-61%, with the device operating in range of 25MHz to 25GHz.This Unicode reader can count the number of vowel, consonants, and digit when used with counter.

[1]  Tanesh Kumar,et al.  Low Power Devnagari Unicode Checker Design Using CGVS Approach , 2014 .

[2]  David Blaauw,et al.  Leakage Current Reduction in VLSI Systems , 2002, J. Circuits Syst. Comput..

[3]  Tanesh Kumar,et al.  Thermal aware energy efficient bengali unicode reader in Text analysis , 2014, 2014 International Conference on Reliability Optimization and Information Technology (ICROIT).

[4]  Gurpreet Singh,et al.  Simulation of CMOS IO Standard Based Energy Efficient Gurmukhi Unicode Reader on FPGA , 2014, 2014 International Conference on Computational Intelligence and Communication Networks.

[5]  Tanesh Kumar,et al.  Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA , 2014, Wirel. Pers. Commun..

[6]  Manisha Pattanaik,et al.  Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA , 2013 .

[7]  Pritam Singh Federalism, Nationalism and Development: India and the Punjab Economy , 2008 .

[8]  Tanesh Kumar,et al.  Design of power optimized memory circuit using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array , 2014, 2014 International Conference on Reliability Optimization and Information Technology (ICROIT).

[9]  B. Pandey,et al.  Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor , 2014, 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE).

[10]  Tanesh Kumar,et al.  I/O standard based power optimized processor register design on ultra scale FPGA , 2014, 2014 International Conference on Computing for Sustainable Global Development (INDIACom).