Low power SRAM design for 14 nm GAA Si-nanowire technology

This paper presents a low power and stable 6-T nanowire SRAM cell design by tuning the extension length of the access transistor. Our approach significantly reduces the power dissipation with a low active area and improves the SRAM cell read stability. We utilize device design parameters such as the nanowire diameter, the number of nanowires, and the device extension length to improve the stability of the SRAM cells. We find that the extension length tuning technique exhibits 15% and ~60% savings in active area and static power consumption, respectively, in comparison to a conventional multi-nanowire tuning technique. In addition, the proposed technique achieves 6% and 8% improvements in the read and hold noise margins, respectively, with a 6.5% decrease in write noise margin and a ~14% increase in the read/write access time. Our results show that the extension length-tuned access transistor is an excellent option for improving the satiability with low power for sub-14-nm technologies.

[1]  W. Fichtner,et al.  Quantum device-simulation with the density-gradient model on unstructured grids , 2001 .

[2]  Per Larsson-Edefors,et al.  Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[3]  Andreas Moshovos,et al.  Low-leakage asymmetric-cell SRAM , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[4]  K. Roy,et al.  Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs , 2011, IEEE Transactions on Electron Devices.

[5]  Mingu Kang,et al.  FinFET SRAM Optimization With Fin Thickness and Surface Orientation , 2010, IEEE Transactions on Electron Devices.

[6]  Yi-Bo Liao,et al.  A high-density SRAM design technique using silicon nanowire FETs , 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

[7]  Siegfried Selberherr,et al.  INFLUENCE OF THE DOPING ELEMENT ON THE ELECTRON MOBILITY IN N-SILICON , 1998 .

[8]  J. Bude,et al.  MOSFET modeling into the ballistic regime , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[9]  M. Motoyoshi,et al.  A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[10]  Borivoje Nikolic,et al.  Large-Scale SRAM Variability Characterization in 45 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[11]  Hui Zhao,et al.  Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation , 2008, IEEE Transactions on Electron Devices.

[12]  S.C. Rustagi,et al.  Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications , 2008, IEEE Transactions on Electron Devices.

[13]  S.C. Rustagi,et al.  Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance , 2006, 2006 International Electron Devices Meeting.

[14]  Jiajing Wang,et al.  Analyzing static and dynamic write margin for nanometer SRAMs , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[15]  Wen-Chin Lee,et al.  Ultimate contact resistance scaling enabled by an accurate contact resistivity extraction methodology for sub-20 nm node , 2006, 2009 Symposium on VLSI Technology.

[16]  Bulusu Anand,et al.  Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic , 2014, IEEE Transactions on Nanotechnology.

[17]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[18]  Sarunya Bangsaruntip,et al.  Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs , 2010, IEEE Electron Device Letters.

[19]  C. Hu,et al.  Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights , 2012, IEEE Transactions on Electron Devices.

[20]  W. Fichtner,et al.  Density gradient transport model for the simulations of ultrathin, ultrashort SOI under non-equilibrium conditions , 2002, 2002 IEEE International SOI Conference.

[21]  Dim-Lee Kwong,et al.  Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach , 2008 .

[22]  Gerard Ghibaudo,et al.  Experimental characterization of the subthreshold leakage current in triple-gate FinFETs , 2009 .

[23]  K. Roy,et al.  Technology and circuit design considerations in quasi-planar double-gate SRAM , 2006, IEEE Transactions on Electron Devices.

[24]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond (Invited Paper) , 2009 .

[25]  Ru Huang,et al.  Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Electron Devices.

[26]  B. Ryu,et al.  Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.

[27]  M. Hasan,et al.  Leakage Characterization of 10T SRAM Cell , 2012, IEEE Transactions on Electron Devices.

[28]  Chao Zhao,et al.  Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate , 2012, IEEE Transactions on Electron Devices.

[29]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[30]  S.C. Rustagi,et al.  CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach , 2007, IEEE Electron Device Letters.